cfg_clock_default_100.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H
25 
26 #include "f2f4f7/cfg_clock_common.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* The following parameters configure a 100MHz system clock with HSE (8MHz, 16MHz or
37  25MHz) or HSI (16MHz) as PLL input clock.
38  If USB is used and no alternative 48MHz is available, the clock frequency is
39  decreased to 96MHZ so the PLLQ can output 48MHz.
40  */
41 #ifndef CONFIG_CLOCK_PLL_M
42 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
43 #define CONFIG_CLOCK_PLL_M (25)
44 #else
45 #define CONFIG_CLOCK_PLL_M (4)
46 #endif
47 #endif
48 #ifndef CONFIG_CLOCK_PLL_N
49 #if IS_USED(MODULE_PERIPH_USBDEV) && defined(CPU_LINE_STM32F411xE)
50 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
51 #define CONFIG_CLOCK_PLL_N (96)
52 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
53 #define CONFIG_CLOCK_PLL_N (192)
54 #else
55 #define CONFIG_CLOCK_PLL_N (48)
56 #endif
57 #else
58 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
59 #define CONFIG_CLOCK_PLL_N (100)
60 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
61 #define CONFIG_CLOCK_PLL_N (200)
62 #else
63 #define CONFIG_CLOCK_PLL_N (50)
64 #endif
65 #endif /* MODULE_PERIPH_USBDEV */
66 #endif
67 #ifndef CONFIG_CLOCK_PLL_P
68 #define CONFIG_CLOCK_PLL_P (2)
69 #endif
70 #ifndef CONFIG_CLOCK_PLL_Q
71 #define CONFIG_CLOCK_PLL_Q (4)
72 #endif
73 #ifndef CONFIG_CLOCK_PLL_R
74 #define CONFIG_CLOCK_PLL_R (4)
75 #endif
76 
81 #ifndef CONFIG_CLOCK_APB1_DIV
82 #define CONFIG_CLOCK_APB1_DIV (2) /* max 50MHz */
83 #endif
84 #ifndef CONFIG_CLOCK_APB2_DIV
85 #define CONFIG_CLOCK_APB2_DIV (1) /* max 100MHz */
86 #endif
87 
89 #ifdef __cplusplus
90 }
91 #endif
92 
93 #include "f2f4f7/cfg_clock_values.h"
94 
95 #if CLOCK_CORECLOCK > MHZ(100)
96 #error "SYSCLK cannot exceed 100MHz"
97 #endif
98 
99 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_100_H */
100 
cfg_clock_common.h
Base STM32F4 clock configuration.
cfg_clock_values.h
STM32F4 clock values definitions.