cfg_clock_default_180.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H
25 
26 #include "f2f4f7/cfg_clock_common.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* The following parameters configure a 180MHz system clock with HSE (8MHz,
37  12MHz or 16MHz) or HSI (16MHz) as PLL input clock.
38  If USB is used and no alternative 48MHz is available, the clock frequency is
39  decreased to 168MHZ so the PLLQ can output 48MHz.
40  */
41 #ifndef CONFIG_CLOCK_PLL_M
42 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
43 #define CONFIG_CLOCK_PLL_M (12)
44 #else
45 #define CONFIG_CLOCK_PLL_M (4)
46 #endif
47 #endif
48 #ifndef CONFIG_CLOCK_PLL_N
49 #if IS_USED(MODULE_PERIPH_USBDEV) && \
50  (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
51  defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
52  defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
53  defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
54 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
55 #define CONFIG_CLOCK_PLL_N (168)
56 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
57 #define CONFIG_CLOCK_PLL_N (336)
58 #else
59 #define CONFIG_CLOCK_PLL_N (84)
60 #endif
61 #else
62 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
63 #define CONFIG_CLOCK_PLL_N (180)
64 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(12))
65 #define CONFIG_CLOCK_PLL_N (360)
66 #else
67 #define CONFIG_CLOCK_PLL_N (90)
68 #endif
69 #endif /* MODULE_PERIPH_USBDEV */
70 #endif
71 #ifndef CONFIG_CLOCK_PLL_P
72 #define CONFIG_CLOCK_PLL_P (2)
73 #endif
74 #ifndef CONFIG_CLOCK_PLL_Q
75 #if IS_USED(MODULE_PERIPH_USBDEV) && \
76  (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
77  defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
78  defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
79  defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F439xx))
80 #define CONFIG_CLOCK_PLL_Q (7)
81 #else
82 #define CONFIG_CLOCK_PLL_Q (8)
83 #endif
84 #endif
85 #ifndef CONFIG_CLOCK_PLL_R
86 #define CONFIG_CLOCK_PLL_R (8)
87 #endif
88 
93 #ifndef CONFIG_CLOCK_APB1_DIV
94 #define CONFIG_CLOCK_APB1_DIV (4) /* max 45MHz */
95 #endif
96 #ifndef CONFIG_CLOCK_APB2_DIV
97 #define CONFIG_CLOCK_APB2_DIV (2) /* max 90MHz */
98 #endif
99 
101 #ifdef __cplusplus
102 }
103 #endif
104 
105 #include "f2f4f7/cfg_clock_values.h"
106 
107 #if CLOCK_CORECLOCK > MHZ(180)
108 #error "SYSCLK cannot exceed 180MHz"
109 #endif
110 
111 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_180_H */
112 
cfg_clock_common.h
Base STM32F4 clock configuration.
cfg_clock_values.h
STM32F4 clock values definitions.