cfg_clock_default_216.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H
25 
26 #include "f2f4f7/cfg_clock_common.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* The following parameters configure a 216MHz system clock with HSE (8MHz,
37  16MHz or 25MHz) or HSI (16MHz) as PLL input clock */
38 #ifndef CONFIG_CLOCK_PLL_M
39 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
40 #define CONFIG_CLOCK_PLL_M (25)
41 #else
42 #define CONFIG_CLOCK_PLL_M (4)
43 #endif
44 #endif
45 #ifndef CONFIG_CLOCK_PLL_N
46 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
47 #define CONFIG_CLOCK_PLL_N (432)
48 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
49 #define CONFIG_CLOCK_PLL_N (216)
50 #else
51 #define CONFIG_CLOCK_PLL_N (108)
52 #endif
53 #endif
54 #ifndef CONFIG_CLOCK_PLL_P
55 #define CONFIG_CLOCK_PLL_P (2)
56 #endif
57 #ifndef CONFIG_CLOCK_PLL_Q
58 #define CONFIG_CLOCK_PLL_Q (9)
59 #endif
60 #ifndef CONFIG_CLOCK_PLL_R
61 #define CONFIG_CLOCK_PLL_R (8)
62 #endif
63 
68 #ifndef CONFIG_CLOCK_APB1_DIV
69 #define CONFIG_CLOCK_APB1_DIV (4) /* max 54MHz */
70 #endif
71 #ifndef CONFIG_CLOCK_APB2_DIV
72 #define CONFIG_CLOCK_APB2_DIV (2) /* max 108MHz */
73 #endif
74 
76 #ifdef __cplusplus
77 }
78 #endif
79 
80 #include "f2f4f7/cfg_clock_values.h"
81 
82 #if CLOCK_CORECLOCK > MHZ(216)
83 #error "SYSCLK cannot exceed 216MHz"
84 #endif
85 
86 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_216_H */
87 
cfg_clock_common.h
Base STM32F4 clock configuration.
cfg_clock_values.h
STM32F4 clock values definitions.