cfg_clock_default_84.h
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1 /*
2  * Copyright (C) 2018 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  * 2018-2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
23 #ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
24 #define CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H
25 
26 #include "f2f4f7/cfg_clock_common.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* The following parameters configure a 84MHz system clock with HSE (8MHz or
37  16MHz) or HSI (16MHz) as PLL input clock */
38 #ifndef CONFIG_CLOCK_PLL_M
39 #define CONFIG_CLOCK_PLL_M (4)
40 #endif
41 #ifndef CONFIG_CLOCK_PLL_N
42 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
43 #define CONFIG_CLOCK_PLL_N (168)
44 #else
45 #define CONFIG_CLOCK_PLL_N (84)
46 #endif
47 #endif
48 #ifndef CONFIG_CLOCK_PLL_P
49 #define CONFIG_CLOCK_PLL_P (4)
50 #endif
51 #ifndef CONFIG_CLOCK_PLL_Q
52 #define CONFIG_CLOCK_PLL_Q (7)
53 #endif
54 #ifndef CONFIG_CLOCK_PLL_R
55 #define CONFIG_CLOCK_PLL_R (0)
56 #endif
57 
62 #ifndef CONFIG_CLOCK_APB1_DIV
63 #define CONFIG_CLOCK_APB1_DIV (2) /* max 42MHz */
64 #endif
65 #ifndef CONFIG_CLOCK_APB2_DIV
66 #define CONFIG_CLOCK_APB2_DIV (1) /* max 84MHz */
67 #endif
68 
70 #ifdef __cplusplus
71 }
72 #endif
73 
74 #include "f2f4f7/cfg_clock_values.h"
75 
76 #if CLOCK_CORECLOCK > MHZ(84)
77 #error "SYSCLK cannot exceed 84MHz"
78 #endif
79 
80 #endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_84_H */
81 
cfg_clock_common.h
Base STM32F4 clock configuration.
cfg_clock_values.h
STM32F4 clock values definitions.