cfg_clock_default.h
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1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CLK_G4_CFG_CLOCK_DEFAULT_H
20 #define CLK_G4_CFG_CLOCK_DEFAULT_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
30 #ifndef CONFIG_USE_CLOCK_PLL
31 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
32 #define CONFIG_USE_CLOCK_PLL 0
33 #else
34 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
35 #endif
36 #endif /* CONFIG_USE_CLOCK_PLL */
37 
38 #ifndef CONFIG_USE_CLOCK_HSE
39 #define CONFIG_USE_CLOCK_HSE 0
40 #endif /* CONFIG_USE_CLOCK_HSE */
41 
42 #ifndef CONFIG_USE_CLOCK_HSI
43 #define CONFIG_USE_CLOCK_HSI 0
44 #endif /* CONFIG_USE_CLOCK_HSI */
45 
46 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
47  (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
48 #error "Cannot use PLL as clock source with other clock configurations"
49 #endif
50 
51 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
52  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
53 #error "Cannot use HSE as clock source with other clock configurations"
54 #endif
55 
56 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
57  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
58 #error "Cannot use HSI as clock source with other clock configurations"
59 #endif
60 
61 #ifndef CONFIG_BOARD_HAS_HSE
62 #define CONFIG_BOARD_HAS_HSE 0
63 #endif
64 #ifndef CLOCK_HSE
65 #define CLOCK_HSE MHZ(24)
66 #endif
67 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
68 #error "HSE clock frequency must be between 4MHz and 48MHz"
69 #endif
70 
71 #ifndef CONFIG_BOARD_HAS_LSE
72 #define CONFIG_BOARD_HAS_LSE 0
73 #endif
74 
75 #define CLOCK_HSI MHZ(16)
76 
77 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
78 #define CLOCK_PLL_SRC (CLOCK_HSE)
79 #else /* CLOCK_HSI */
80 #define CLOCK_PLL_SRC (CLOCK_HSI)
81 #endif
82 
83 /* The following parameters configure a 170MHz system clock with HSI16 as input clock */
84 #ifndef CONFIG_CLOCK_PLL_M
85 #define CONFIG_CLOCK_PLL_M (4)
86 #endif
87 #ifndef CONFIG_CLOCK_PLL_N
88 #define CONFIG_CLOCK_PLL_N (85)
89 #endif
90 #ifndef CONFIG_CLOCK_PLL_R
91 #define CONFIG_CLOCK_PLL_R (2)
92 #endif
93 
94 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
95 #define CLOCK_CORECLOCK (CLOCK_HSI)
96 
97 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
98 #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
99 #error "The board doesn't provide an HSE oscillator"
100 #endif
101 #define CLOCK_CORECLOCK (CLOCK_HSE)
102 
103 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
104 #define CLOCK_CORECLOCK \
105  ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
106 #if CLOCK_CORECLOCK > MHZ(170)
107 #error "SYSCLK cannot exceed 170MHz"
108 #endif
109 #endif /* CONFIG_USE_CLOCK_PLL */
110 
111 #define CLOCK_AHB CLOCK_CORECLOCK /* max: 170MHz */
112 
113 #ifndef CONFIG_CLOCK_APB1_DIV
114 #define CONFIG_CLOCK_APB1_DIV (1)
115 #endif
116 #define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
117 #ifndef CONFIG_CLOCK_APB2_DIV
118 #define CONFIG_CLOCK_APB2_DIV (1)
119 #endif
120 #define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
121 
122 #ifdef __cplusplus
123 }
124 #endif
125 
126 #endif /* CLK_G4_CFG_CLOCK_DEFAULT_H */
127