cfg_clock_default.h
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1 /*
2  * Copyright (C) 2017 Freie Universität Berlin
3  * 2019 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
22 #define CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #ifndef CONFIG_USE_CLOCK_PLL
33 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
34  IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
35 #define CONFIG_USE_CLOCK_PLL 0
36 #else
37 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
38 #endif
39 #endif /* CONFIG_USE_CLOCK_PLL */
40 
41 #ifndef CONFIG_USE_CLOCK_MSI
42 #define CONFIG_USE_CLOCK_MSI 0
43 #endif /* CONFIG_USE_CLOCK_MSI */
44 
45 #ifndef CONFIG_USE_CLOCK_HSE
46 #define CONFIG_USE_CLOCK_HSE 0
47 #endif /* CONFIG_USE_CLOCK_HSE */
48 
49 #ifndef CONFIG_USE_CLOCK_HSI
50 #define CONFIG_USE_CLOCK_HSI 0
51 #endif /* CONFIG_USE_CLOCK_HSI */
52 
53 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
54  (IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
55  IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
56 #error "Cannot use PLL as clock source with other clock configurations"
57 #endif
58 
59 #if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
60  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
61  IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
62 #error "Cannot use MSI as clock source with other clock configurations"
63 #endif
64 
65 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
66  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
67  IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
68 #error "Cannot use HSE as clock source with other clock configurations"
69 #endif
70 
71 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
72  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
73  IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
74 #error "Cannot use HSI as clock source with other clock configurations"
75 #endif
76 
77 #ifndef CONFIG_BOARD_HAS_HSE
78 #define CONFIG_BOARD_HAS_HSE 0
79 #endif
80 #ifndef CLOCK_HSE
81 #define CLOCK_HSE MHZ(8)
82 #endif
83 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
84 #error "HSE clock frequency must be between 4MHz and 48MHz"
85 #endif
86 
87 #ifndef CONFIG_BOARD_HAS_LSE
88 #define CONFIG_BOARD_HAS_LSE 0
89 #endif
90 
91 #define CLOCK_HSI MHZ(16)
92 
93 #ifndef CONFIG_CLOCK_MSI
94 #define CONFIG_CLOCK_MSI MHZ(48)
95 #endif
96 
97 /* The following parameters configure a 80MHz system clock with PLL as input clock */
98 #ifndef CONFIG_CLOCK_PLL_SRC_MSI
99 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
100  IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
101 #define CONFIG_CLOCK_PLL_SRC_MSI 0
102 #else
103 #define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
104 #endif
105 #endif /* CONFIG_CLOCK_PLL_SRC_MSI */
106 #ifndef CONFIG_CLOCK_PLL_SRC_HSE
107 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
108  !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
109 #define CONFIG_CLOCK_PLL_SRC_HSE 1
110 #else
111 #define CONFIG_CLOCK_PLL_SRC_HSE 0
112 #endif
113 #endif
114 #ifndef CONFIG_CLOCK_PLL_SRC_HSI
115 #define CONFIG_CLOCK_PLL_SRC_HSI 0
116 #endif
117 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
118 #define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
119 #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
120 #define CLOCK_PLL_SRC (CLOCK_HSE)
121 #else /* CONFIG_CLOCK_PLL_SRC_ */
122 #define CLOCK_PLL_SRC (CLOCK_HSI)
123 #endif
124 #ifndef CONFIG_CLOCK_PLL_M
125 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
126 #define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
127 #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(8))
128 #define CONFIG_CLOCK_PLL_M (1) /* HSE at 8MHz */
129 #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32))
130 #define CONFIG_CLOCK_PLL_M (4) /* HSE at 32MHz */
131 #else
132 #define CONFIG_CLOCK_PLL_M (2) /* HSI at 16MHz */
133 #endif
134 #endif
135 #ifndef CONFIG_CLOCK_PLL_N
136 #if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(32))
137 #define CONFIG_CLOCK_PLL_N (16)
138 #elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
139  (IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) && (CLOCK_HSE == MHZ(16)))
140 #define CONFIG_CLOCK_PLL_N (32)
141 #else
142 #if defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
143  defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
144  defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
145  defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
146  defined(CPU_LINE_STM32L4S9xx)
147 #define CONFIG_CLOCK_PLL_N (30)
148 #elif defined(CPU_FAM_STM32L5)
149 #define CONFIG_CLOCK_PLL_N (27)
150 #else
151 #define CONFIG_CLOCK_PLL_N (20)
152 #endif
153 #endif
154 #endif
155 #ifndef CONFIG_CLOCK_PLL_Q
156 #define CONFIG_CLOCK_PLL_Q (2)
157 #endif
158 #ifndef CONFIG_CLOCK_PLL_R
159 #define CONFIG_CLOCK_PLL_R (2)
160 #endif
161 
162 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
163 #define CLOCK_CORECLOCK (CLOCK_HSI)
164 
165 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
166 #define CLOCK_CORECLOCK (CLOCK_HSE)
167 
168 #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
169 #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
170 
171 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
172 /* PLL configuration: make sure your values are legit!
173  *
174  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
175  * with:
176  * PLL_IN: input clock, HSE or MSI
177  * M: pre-divider, allowed range: [1:8]
178  * N: multiplier, allowed range: [8:86]
179  * R: post-divider, allowed range: [2:8]
180  *
181  * Also the following constraints need to be met:
182  * (PLL_IN / M) -> [4MHz:16MHz]
183  * (PLL_IN / M) * N -> [64MHz:344MHz]
184  * CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
185  */
186 #define CLOCK_CORECLOCK \
187  ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
188 
189 /* Set max allowed sysclk */
190 #if defined(CPU_FAM_STM32WB)
191 #define CLOCK_CORECLOCK_MAX MHZ(64)
192 #elif defined(CPU_FAM_STM32L5)
193 #define CLOCK_CORECLOCK_MAX MHZ(110)
194 #elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
195  defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
196  defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
197  defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
198  defined(CPU_LINE_STM32L4S9xx)
199 #define CLOCK_CORECLOCK_MAX MHZ(120)
200 #else /* all the other L4 */
201 #define CLOCK_CORECLOCK_MAX MHZ(80)
202 #endif
203 
204 #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
205 #if CLOCK_CORECLOCK_MAX == MHZ(64)
206 #error "SYSCLK cannot exceed 64MHz"
207 #elif CLOCK_CORECLOCK_MAX == MHZ(80)
208 #error "SYSCLK cannot exceed 80MHz"
209 #elif CLOCK_CORECLOCK_MAX == MHZ(110)
210 #error "SYSCLK cannot exceed 110MHz"
211 #elif CLOCK_CORECLOCK_MAX == MHZ(120)
212 #error "SYSCLK cannot exceed 120MHz"
213 #else
214 #error "invalid SYSCLK"
215 #endif
216 #endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
217 #endif /* CONFIG_USE_CLOCK_PLL */
218 
219 #define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 64/80/120MHz */
220 
221 #ifndef CONFIG_CLOCK_APB1_DIV
222 #define CONFIG_CLOCK_APB1_DIV (4)
223 #endif
224 #define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 64/80/120MHz */
225 #ifndef CONFIG_CLOCK_APB2_DIV
226 #define CONFIG_CLOCK_APB2_DIV (2)
227 #endif
228 #define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 64/80/120MHz */
229 
230 #ifdef __cplusplus
231 }
232 #endif
233 
234 #endif /* CLK_L4L5WB_CFG_CLOCK_DEFAULT_H */
235