cpu_conf_kinetis.h
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1 /*
2  * Copyright (C) 2017 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CPU_CONF_KINETIS_H
20 #define CPU_CONF_KINETIS_H
21 
22 #include "cpu_conf_common.h"
23 
24 #if (__CORTEX_M < 3)
25 /*
26  * Kinetis Cortex-M0+ devices have bit manipulation engine (BME) which provides
27  * the same functionality (and some more) as the bitband aliased memory found in
28  * Cortex-M3 and up
29  */
30 #include "bme.h"
31 #endif
32 
33 #ifdef __cplusplus
34 extern "C"
35 {
36 #endif
37 
42 #define CPU_DEFAULT_IRQ_PRIO (1U)
43 #define CPU_IRQ_NUMOF (NUMBER_OF_INT_VECTORS)
44 #define CPU_FLASH_BASE (0x00000000)
45 
51 #define PIN_MUX_FUNCTION_ANALOG 0
52 #define PIN_MUX_FUNCTION_GPIO 1
53 
59 #define PIN_INTERRUPT_RISING 0b1001
60 #define PIN_INTERRUPT_FALLING 0b1010
61 #define PIN_INTERRUPT_EDGE 0b1011
62 
68 /* Different versions of vendor headers use some variations of register names.
69  * This section aims to eliminate these differences in the few places where it
70  * matters for the RIOT driver implementations.
71  */
72 #if !defined(MCG_C2_RANGE0) && defined(MCG_C2_RANGE)
73 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
74 #endif
75 #if !defined(MCG_C2_RANGE0_MASK) && defined(MCG_C2_RANGE_MASK)
76 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
77 #endif
78 #if !defined(MCG_C7_OSCSEL) && defined(MCG_C7_OSCSEL_SHIFT)
79 #define MCG_C7_OSCSEL(x) (((uint32_t)(x) << MCG_C7_OSCSEL_SHIFT) & MCG_C7_OSCSEL_MASK)
80 #endif
81 #if !defined(OSC0) && defined(OSC)
82 #define OSC0 OSC
83 #endif
84 #if !defined(SIM_SOPT2_LPUART0SRC_MASK) && defined(SIM_SOPT2_LPUARTSRC_MASK)
85 #define SIM_SOPT2_LPUART0SRC_MASK SIM_SOPT2_LPUARTSRC_MASK
86 #define SIM_SOPT2_LPUART0SRC_SHIFT SIM_SOPT2_LPUARTSRC_SHIFT
87 #define SIM_SOPT2_LPUART0SRC SIM_SOPT2_LPUARTSRC
88 #endif
89 #if !defined(SIM_SCGC5_LPTMR_SHIFT) && defined(SIM_SCGC5_LPTIMER_SHIFT)
90 #define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
91 #endif
92 #if !defined(SIM_SCGC5_LPTMR_MASK) && defined(SIM_SCGC5_LPTIMER_MASK)
93 #define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
94 #endif
95 #if !defined(GPIOA_BASE) && defined(PTA_BASE)
96 #define GPIOA_BASE PTA_BASE
97 #define GPIOB_BASE PTB_BASE
98 #define GPIOC_BASE PTC_BASE
99 #define GPIOD_BASE PTD_BASE
100 #define GPIOE_BASE PTE_BASE
101 #define GPIOF_BASE PTF_BASE
102 #define GPIOG_BASE PTG_BASE
103 #endif
104 #if !defined(GPIOA) && defined(PTA)
105 #define GPIOA PTA
106 #define GPIOB PTB
107 #define GPIOC PTC
108 #define GPIOD PTD
109 #define GPIOE PTE
110 #define GPIOF PTF
111 #define GPIOG PTG
112 #endif
113 
119 #ifdef SIM_SCGC5_LPTMR_SHIFT
120 
121 #define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))
122 #endif
123 #if defined(SIM_SCGC6_PIT_SHIFT)
124 
125 #define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
126 #elif defined(SIM_SCGC_PIT_SHIFT)
127 #define PIT_CLKEN() (bit_set32(&SIM->SCGC, SIM_SCGC_PIT_SHIFT))
128 #endif
129 #ifdef SIM_SCGC6_RTC_SHIFT
130 
131 #define RTC_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_RTC_SHIFT))
132 #endif
133 
139 #ifdef SIM_SCGC4_I2C0_SHIFT
140 
141 #define I2C0_CLKEN() (bit_set32(&SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT))
142 #endif
143 #ifdef SIM_SCGC4_I2C1_SHIFT
144 
145 #define I2C1_CLKEN() (bit_set32(&SIM->SCGC4, SIM_SCGC4_I2C1_SHIFT))
146 #endif
147 #ifdef SIM_SCGC1_I2C2_SHIFT
148 
149 #define I2C2_CLKEN() (bit_set32(&SIM->SCGC1, SIM_SCGC1_I2C2_SHIFT))
150 #endif
151 
157 #if !defined(HWRNG_CLK_REG) && !defined(HWRNG_CLK_REG_SHIFT)
158 #if defined(SIM_SCGC3_RNGA_SHIFT)
159 #define HWRNG_CLK_REG SIM->SCGC3
160 #define HWRNG_CLK_REG_SHIFT SIM_SCGC3_RNGA_SHIFT
161 #elif defined(SIM_SCGC6_RNGA_SHIFT)
162 #define HWRNG_CLK_REG SIM->SCGC6
163 #define HWRNG_CLK_REG_SHIFT SIM_SCGC6_RNGA_SHIFT
164 #endif
165 #endif
166 #if defined(RNG)
167 #define KINETIS_RNGA RNG
168 #define HWRNG_CLKEN() (bit_set32(&HWRNG_CLK_REG, HWRNG_CLK_REG_SHIFT))
169 #define HWRNG_CLKDIS() (bit_clear32(&HWRNG_CLK_REG, HWRNG_CLK_REG_SHIFT))
170 #endif /* KINETIS_RNGA */
171 
177 #if defined(MK20D7_H_)
178 #define LLWU_IRQn LLW_IRQn
179 #define LPTMR0_IRQn LPTimer_IRQn
180 #define PIT_TCTRL_CHN_MASK (0x4u)
181 #define PIT_TCTRL_CHN_SHIFT (2)
182 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
183 #endif /* MK20D7_H_ */
184 
187 #ifdef __cplusplus
188 }
189 #endif
190 
191 #endif /* CPU_CONF_KINETIS_H */
192 
bme.h
Macro definitions for the Kinetis Bit Manipulation Engine (BME)