vendor_conf.h
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1 /**************************************************************************/
26 #if !defined(VENDOR_CONF_H) && !DOXYGEN
27 #define VENDOR_CONF_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
33 /*--------------------- Clock Configuration ----------------------------------
34  *
35  * <e> Clock Configuration
36  * <h> System Controls and Status Register (SCS)
37  * <o1.4> OSCRANGE: Main Oscillator Range Select
38  * <0=> 1 MHz to 20 MHz
39  * <1=> 15 MHz to 24 MHz
40  * <e1.5> OSCEN: Main Oscillator Enable
41  * </e>
42  * </h>
43  *
44  * <h> Clock Source Select Register (CLKSRCSEL)
45  * <o2.0..1> CLKSRC: PLL Clock Source Selection
46  * <0=> Internal RC oscillator
47  * <1=> Main oscillator
48  * <2=> RTC oscillator
49  * </h>
50  *
51  * <e3> PLL0 Configuration (Main PLL)
52  * <h> PLL0 Configuration Register (PLL0CFG)
53  * <i> F_cco0 = (2 * M * F_in) / N
54  * <i> F_in must be in the range of 32 kHz to 50 MHz
55  * <i> F_cco0 must be in the range of 275 MHz to 550 MHz
56  * <o4.0..14> MSEL: PLL Multiplier Selection
57  * <6-32768><#-1>
58  * <i> M Value
59  * <o4.16..23> NSEL: PLL Divider Selection
60  * <1-256><#-1>
61  * <i> N Value
62  * </h>
63  * </e>
64  *
65  * <e5> PLL1 Configuration (USB PLL)
66  * <h> PLL1 Configuration Register (PLL1CFG)
67  * <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
68  * <i> F_cco1 = F_osc * M * 2 * P
69  * <i> F_cco1 must be in the range of 156 MHz to 320 MHz
70  * <o6.0..4> MSEL: PLL Multiplier Selection
71  * <1-32><#-1>
72  * <i> M Value (for USB maximum value is 4)
73  * <o6.5..6> PSEL: PLL Divider Selection
74  * <0=> 1
75  * <1=> 2
76  * <2=> 4
77  * <3=> 8
78  * <i> P Value
79  * </h>
80  * </e>
81  *
82  * <h> CPU Clock Configuration Register (CCLKCFG)
83  * <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
84  * <1-256><#-1>
85  * </h>
86  *
87  * <h> USB Clock Configuration Register (USBCLKCFG)
88  * <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
89  * <0-15>
90  * <i> Divide is USBSEL + 1
91  * </h>
92  *
93  * <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
94  * <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
95  * <0=> Pclk = Cclk / 4
96  * <1=> Pclk = Cclk
97  * <2=> Pclk = Cclk / 2
98  * <3=> Pclk = Hclk / 8
99  * <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
100  * <0=> Pclk = Cclk / 4
101  * <1=> Pclk = Cclk
102  * <2=> Pclk = Cclk / 2
103  * <3=> Pclk = Hclk / 8
104  * <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
105  * <0=> Pclk = Cclk / 4
106  * <1=> Pclk = Cclk
107  * <2=> Pclk = Cclk / 2
108  * <3=> Pclk = Hclk / 8
109  * <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
110  * <0=> Pclk = Cclk / 4
111  * <1=> Pclk = Cclk
112  * <2=> Pclk = Cclk / 2
113  * <3=> Pclk = Hclk / 8
114  * <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
115  * <0=> Pclk = Cclk / 4
116  * <1=> Pclk = Cclk
117  * <2=> Pclk = Cclk / 2
118  * <3=> Pclk = Hclk / 8
119  * <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
120  * <0=> Pclk = Cclk / 4
121  * <1=> Pclk = Cclk
122  * <2=> Pclk = Cclk / 2
123  * <3=> Pclk = Hclk / 8
124  * <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
125  * <0=> Pclk = Cclk / 4
126  * <1=> Pclk = Cclk
127  * <2=> Pclk = Cclk / 2
128  * <3=> Pclk = Hclk / 8
129  * <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
130  * <0=> Pclk = Cclk / 4
131  * <1=> Pclk = Cclk
132  * <2=> Pclk = Cclk / 2
133  * <3=> Pclk = Hclk / 8
134  * <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
135  * <0=> Pclk = Cclk / 4
136  * <1=> Pclk = Cclk
137  * <2=> Pclk = Cclk / 2
138  * <3=> Pclk = Hclk / 8
139  * <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
140  * <0=> Pclk = Cclk / 4
141  * <1=> Pclk = Cclk
142  * <2=> Pclk = Cclk / 2
143  * <3=> Pclk = Hclk / 8
144  * <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
145  * <0=> Pclk = Cclk / 4
146  * <1=> Pclk = Cclk
147  * <2=> Pclk = Cclk / 2
148  * <3=> Pclk = Hclk / 8
149  * <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
150  * <0=> Pclk = Cclk / 4
151  * <1=> Pclk = Cclk
152  * <2=> Pclk = Cclk / 2
153  * <3=> Pclk = Hclk / 6
154  * <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
155  * <0=> Pclk = Cclk / 4
156  * <1=> Pclk = Cclk
157  * <2=> Pclk = Cclk / 2
158  * <3=> Pclk = Hclk / 6
159  * <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
160  * <0=> Pclk = Cclk / 4
161  * <1=> Pclk = Cclk
162  * <2=> Pclk = Cclk / 2
163  * <3=> Pclk = Hclk / 6
164  * </h>
165  *
166  * <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
167  * <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
168  * <0=> Pclk = Cclk / 4
169  * <1=> Pclk = Cclk
170  * <2=> Pclk = Cclk / 2
171  * <3=> Pclk = Hclk / 8
172  * <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
173  * <0=> Pclk = Cclk / 4
174  * <1=> Pclk = Cclk
175  * <2=> Pclk = Cclk / 2
176  * <3=> Pclk = Hclk / 8
177  * <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
178  * <0=> Pclk = Cclk / 4
179  * <1=> Pclk = Cclk
180  * <2=> Pclk = Cclk / 2
181  * <3=> Pclk = Hclk / 8
182  * <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
183  * <0=> Pclk = Cclk / 4
184  * <1=> Pclk = Cclk
185  * <2=> Pclk = Cclk / 2
186  * <3=> Pclk = Hclk / 8
187  * <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
188  * <0=> Pclk = Cclk / 4
189  * <1=> Pclk = Cclk
190  * <2=> Pclk = Cclk / 2
191  * <3=> Pclk = Hclk / 8
192  * <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
193  * <0=> Pclk = Cclk / 4
194  * <1=> Pclk = Cclk
195  * <2=> Pclk = Cclk / 2
196  * <3=> Pclk = Hclk / 8
197  * <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
198  * <0=> Pclk = Cclk / 4
199  * <1=> Pclk = Cclk
200  * <2=> Pclk = Cclk / 2
201  * <3=> Pclk = Hclk / 8
202  * <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
203  * <0=> Pclk = Cclk / 4
204  * <1=> Pclk = Cclk
205  * <2=> Pclk = Cclk / 2
206  * <3=> Pclk = Hclk / 8
207  * <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
208  * <0=> Pclk = Cclk / 4
209  * <1=> Pclk = Cclk
210  * <2=> Pclk = Cclk / 2
211  * <3=> Pclk = Hclk / 8
212  * <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
213  * <0=> Pclk = Cclk / 4
214  * <1=> Pclk = Cclk
215  * <2=> Pclk = Cclk / 2
216  * <3=> Pclk = Hclk / 8
217  * <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
218  * <0=> Pclk = Cclk / 4
219  * <1=> Pclk = Cclk
220  * <2=> Pclk = Cclk / 2
221  * <3=> Pclk = Hclk / 8
222  * <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
223  * <0=> Pclk = Cclk / 4
224  * <1=> Pclk = Cclk
225  * <2=> Pclk = Cclk / 2
226  * <3=> Pclk = Hclk / 8
227  * <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
228  * <0=> Pclk = Cclk / 4
229  * <1=> Pclk = Cclk
230  * <2=> Pclk = Cclk / 2
231  * <3=> Pclk = Hclk / 8
232  * <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
233  * <0=> Pclk = Cclk / 4
234  * <1=> Pclk = Cclk
235  * <2=> Pclk = Cclk / 2
236  * <3=> Pclk = Hclk / 8
237  * </h>
238  *
239  * <h> Power Control for Peripherals Register (PCONP)
240  * <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
241  * <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
242  * <o11.3> PCUART0: UART 0 power/clock enable
243  * <o11.4> PCUART1: UART 1 power/clock enable
244  * <o11.6> PCPWM1: PWM 1 power/clock enable
245  * <o11.7> PCI2C0: I2C interface 0 power/clock enable
246  * <o11.8> PCSPI: SPI interface power/clock enable
247  * <o11.9> PCRTC: RTC power/clock enable
248  * <o11.10> PCSSP1: SSP interface 1 power/clock enable
249  * <o11.12> PCAD: A/D converter power/clock enable
250  * <o11.13> PCCAN1: CAN controller 1 power/clock enable
251  * <o11.14> PCCAN2: CAN controller 2 power/clock enable
252  * <o11.15> PCGPIO: GPIOs power/clock enable
253  * <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
254  * <o11.17> PCMC: Motor control PWM power/clock enable
255  * <o11.18> PCQEI: Quadrature encoder interface power/clock enable
256  * <o11.19> PCI2C1: I2C interface 1 power/clock enable
257  * <o11.21> PCSSP0: SSP interface 0 power/clock enable
258  * <o11.22> PCTIM2: Timer 2 power/clock enable
259  * <o11.23> PCTIM3: Timer 3 power/clock enable
260  * <o11.24> PCUART2: UART 2 power/clock enable
261  * <o11.25> PCUART3: UART 3 power/clock enable
262  * <o11.26> PCI2C2: I2C interface 2 power/clock enable
263  * <o11.27> PCI2S: I2S interface power/clock enable
264  * <o11.29> PCGPDMA: GP DMA function power/clock enable
265  * <o11.30> PCENET: Ethernet block power/clock enable
266  * <o11.31> PCUSB: USB interface power/clock enable
267  * </h>
268  *
269  * <h> Clock Output Configuration Register (CLKOUTCFG)
270  * <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
271  * <0=> CPU clock
272  * <1=> Main oscillator
273  * <2=> Internal RC oscillator
274  * <3=> USB clock
275  * <4=> RTC oscillator
276  * <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
277  * <1-16><#-1>
278  * <o12.8> CLKOUT_EN: CLKOUT enable control
279  * </h>
280  *
281  * </e>
282  */
283 #define CLOCK_SETUP 1
284 #define SCS_Val 0x00000020
285 #define CLKSRCSEL_Val 0x00000001
286 #define PLL0_SETUP 1
287 #define PLL0CFG_Val 0x00050063
288 #define PLL1_SETUP 1
289 #define PLL1CFG_Val 0x00000023
290 #define CCLKCFG_Val 0x00000003
291 #define USBCLKCFG_Val 0x00000000
292 #define PCLKSEL0_Val 0x00000000
293 #define PCLKSEL1_Val 0x00000000
294 #define PCONP_Val 0x042887DE
295 #define CLKOUTCFG_Val 0x00000000
296 
297 
298 /* --------------------- Flash Accelerator Configuration ----------------------
299  *
300  * <e> Flash Accelerator Configuration
301  * <o1.12..15> FLASHTIM: Flash Access Time
302  * <0=> 1 CPU clock (for CPU clock up to 20 MHz)
303  * <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
304  * <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
305  * <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
306  * <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
307  * <5=> 6 CPU clocks (for any CPU clock)
308  * </e>
309  */
310 #define FLASH_SETUP 1
311 #define FLASHCFG_Val 0x00004000
312 
313 /*
314  * -------- <<< end of configuration section >>> ------------------------------
315  */
316 
317 /*
318  * Check the register settings
319  */
320 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
321 #define CHECK_RSVD(val, mask) (val & mask)
322 
323 /* Clock Configuration */
324 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
325 #error "SCS: Invalid values of reserved bits!"
326 #endif
327 
328 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
329 #error "CLKSRCSEL: Value out of range!"
330 #endif
331 
332 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
333 #error "PLL0CFG: Invalid values of reserved bits!"
334 #endif
335 
336 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
337 #error "PLL1CFG: Invalid values of reserved bits!"
338 #endif
339 
340 #if (PLL0_SETUP) /* if PLL0 is used */
341 #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
342 #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
343 #endif
344 #endif
345 
346 #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
347 #error "CCLKCFG: Value out of range!"
348 #endif
349 
350 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
351 #error "USBCLKCFG: Invalid values of reserved bits!"
352 #endif
353 
354 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
355 #error "PCLKSEL0: Invalid values of reserved bits!"
356 #endif
357 
358 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
359 #error "PCLKSEL1: Invalid values of reserved bits!"
360 #endif
361 
362 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
363 #error "PCONP: Invalid values of reserved bits!"
364 #endif
365 
366 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
367 #error "CLKOUTCFG: Invalid values of reserved bits!"
368 #endif
369 
370 /* Flash Accelerator Configuration */
371 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
372 #error "FLASHCFG: Invalid values of reserved bits!"
373 #endif
374 
375 
376 /*
377  * DEFINES
378  */
379 
380 /*
381  * Define clocks
382  */
383 #define XTAL (12000000UL) /* Oscillator frequency */
384 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
385 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
386 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
387 
388 
389 /* F_cco0 = (2 * M * F_in) / N */
390 #define _M_ (((PLL0CFG_Val ) & 0x7FFF) + 1)
391 #define _N_ (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
392 #define FCCO(F_IN) ((2ULL * _M_ * F_IN) / _N_)
393 #define CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
394 
395 /* Determine core clock frequency according to settings */
396 #if (PLL0_SETUP)
397 #if ((CLKSRCSEL_Val & 0x03) == 1)
398 #define CLOCK_CORECLOCK (FCCO(OSC_CLK) / CCLK_DIV)
399 #elif ((CLKSRCSEL_Val & 0x03) == 2)
400 #define CLOCK_CORECLOCK (FCCO(RTC_CLK) / CCLK_DIV)
401 #else
402 #define CLOCK_CORECLOCK (FCCO(IRC_OSC) / CCLK_DIV)
403 #endif
404 #else
405 #if ((CLKSRCSEL_Val & 0x03) == 1)
406 #define CLOCK_CORECLOCK (OSC_CLK / CCLK_DIV)
407 #elif ((CLKSRCSEL_Val & 0x03) == 2)
408 #define CLOCK_CORECLOCK (RTC_CLK / CCLK_DIV)
409 #else
410 #define CLOCK_CORECLOCK (IRC_OSC / CCLK_DIV)
411 #endif
412 #endif
413 
414 #ifdef __cplusplus
415 }
416 #endif
417 
418 #endif /* VENDOR_CONF_H */
419