board.h
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1 /*
2  * Copyright (C) 2017 Thomas Stilwell <stilwellt@openlabs.co>
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
20 #ifndef BOARD_H
21 #define BOARD_H
22 
23 #include "cpu.h"
24 #include "periph_conf.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
31 /*
32  * NMI shares a pin with DAC output and ADC input. Holding the pin low during
33  * reset will cause a hang unless NMI is disabled. It can be enabled in
34  * applications where the pin is not held low during reset.
35  */
36 #define KINETIS_FOPT 0xFB /* disable NMI (0xFF to enable) */
37 
42 #define LED0_PIN GPIO_PIN(PORT_B, 0)
43 #define LED0_MASK (1 << 0)
44 #define LED0_ON (GPIOB->PCOR = LED0_MASK)
45 #define LED0_OFF (GPIOB->PSOR = LED0_MASK)
46 #define LED0_TOGGLE (GPIOB->PTOR = LED0_MASK)
47 
53 #if KINETIS_XTIMER_SOURCE_PIT
54 /* PIT xtimer configuration */
55 #define XTIMER_DEV (TIMER_PIT_DEV(0))
56 #define XTIMER_CHAN (0)
57 /* Default xtimer settings should work on the PIT */
58 #else
59 /* LPTMR xtimer configuration */
60 #define XTIMER_DEV (TIMER_LPTMR_DEV(0))
61 #define XTIMER_CHAN (0)
62 /* LPTMR is 16 bits wide and runs at 32768 Hz (clocked by the RTC) */
63 #define XTIMER_WIDTH (16)
64 #define XTIMER_BACKOFF (16)
65 #define XTIMER_ISR_BACKOFF (5)
66 #define XTIMER_HZ (32768ul)
67 #endif
68 
75 #ifndef PTB3_OUTPUT_OSC32K
76 #define PTB3_OUTPUT_OSC32K (0)
77 #endif
78 
84 #ifndef PTB3_OUTPUT_OSCERCLK
85 #define PTB3_OUTPUT_OSCERCLK (0)
86 #endif
87 
91 void board_init(void);
92 
93 #ifdef __cplusplus
94 }
95 #endif
96 
97 #endif /* BOARD_H */
98 
periph_conf.h
board_init
void board_init(void)
Board level initialization.