cpu_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include "cpu_conf_common.h"
25 
26 /* Workaround redefinition of LITTLE_ENDIAN macro (part1) */
27 #ifdef LITTLE_ENDIAN
28 #define __TMP_LITTLE_ENDIAN LITTLE_ENDIAN
29 #undef LITTLE_ENDIAN
30 #endif
31 
32 #if defined(CPU_SAMD21A)
33 #include "vendor/samd21/include_a/samd21.h"
34 #elif defined(CPU_SAMD21B)
35 #include "vendor/samd21/include_b/samd21.h"
36 #elif defined(CPU_SAMD21C)
37 #include "vendor/samd21/include_c/samd21.h"
38 #elif defined(CPU_SAMD21D)
39 #include "vendor/samd21/include_d/samd21.h"
40 #elif defined(CPU_SAMD51)
41 #include "vendor/samd51/include/samd51.h"
42 #elif defined(CPU_SAME54)
43 #include "vendor/same54/include/same54.h"
44 #elif defined(CPU_SAML10)
45 #include "vendor/saml10/include/sam.h"
46 #elif defined(CPU_SAML11)
47 #include "vendor/saml11/include/sam.h"
48 #elif defined(CPU_SAML21A)
49 #include "vendor/saml21/include/saml21.h"
50 #elif defined(CPU_SAML21B)
51 #include "vendor/saml21/include_b/saml21.h"
52 #elif defined(CPU_SAMR21)
53 #include "vendor/samr21/include/samr21.h"
54 #elif defined(CPU_SAMR30)
55 #include "vendor/samr30/include/samr30.h"
56 #elif defined(CPU_SAMR34)
57 #include "vendor/samr34/include/samr34.h"
58 #endif
59 
60 /* Workaround redefinition of LITTLE_ENDIAN macro (part2) */
61 #ifdef LITTLE_ENDIAN
62 #undef LITTLE_ENDIAN
63 #endif
64 
65 #ifdef __TMP_LITTLE_ENDIAN
66 #define LITTLE_ENDIAN __TMP_LITTLE_ENDIAN
67 #endif
68 
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72 
77 #define CPU_DEFAULT_IRQ_PRIO (1U)
78 #define CPU_IRQ_NUMOF PERIPH_COUNT_IRQn
79 #define CPU_FLASH_BASE FLASH_ADDR
80 
81 #ifdef CPU_COMMON_SAML1X
82 #define CPU_FLASH_RWWEE_BASE DATAFLASH_ADDR
83 #else
84 #define CPU_FLASH_RWWEE_BASE NVMCTRL_RWW_EEPROM_ADDR
85 #endif
86 
92 /* a flashpage in RIOT is mapped to a flash row on the SAM0s */
93 #if defined(NVMCTRL_ROW_SIZE)
94 #define FLASHPAGE_SIZE (NVMCTRL_ROW_SIZE)
95 #elif defined(NVMCTRL_BLOCK_SIZE)
96 #define FLASHPAGE_SIZE (NVMCTRL_BLOCK_SIZE)
97 #elif defined(NVMCTRL_PAGE_SIZE)
98 /* saml1x: The NVM is organized into rows, where each row contains four pages,
99 as shown in the NVM Row Organization figure. */
100 #define FLASHPAGE_SIZE (4 * NVMCTRL_PAGE_SIZE)
101 #else
102 #error "Unsupported Device"
103 #endif
104 
105 /* one SAM0 row contains 4 SAM0 pages, so 4 SAM0 pages contain
106  * the amount of a RIOT flashpage
107  */
108 #define FLASHPAGE_PAGES_PER_ROW (FLASHPAGE_SIZE/FLASH_PAGE_SIZE)
109 /* number of RIOT flashpages on device */
110 #define FLASHPAGE_NUMOF (FLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
111 /* The minimum block size which can be written is 16B. However, the erase
112  * block is always FLASHPAGE_SIZE (SAM0 row).
113  */
114 #define FLASHPAGE_WRITE_BLOCK_SIZE (16)
115 /* Writing should be always 4 byte aligned */
116 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4)
117 /* Add RWWEE memory if supported by revision of the chip
118  * On some chips it is called RWW EEPROM while on some DATAFLASH, try to
119  * catch all without relying on the CPU model but on the named defines
120  */
121 #ifdef NVMCTRL_RWW_EEPROM_SIZE
122 #define FLASHPAGE_RWWEE_NUMOF (NVMCTRL_RWWEE_PAGES / FLASHPAGE_PAGES_PER_ROW)
123 #endif
124 #ifdef DATAFLASH_SIZE
125 #define FLASHPAGE_RWWEE_NUMOF (DATAFLASH_NB_OF_PAGES / FLASHPAGE_PAGES_PER_ROW)
126 #endif
127 
132 #ifdef CPU_HAS_BACKUP_RAM
133 #define NUM_HEAPS (2)
134 #endif
135 
136 #ifdef __cplusplus
137 }
138 #endif
139 
140 #endif /* CPU_CONF_H */
141