stmpe811_constants.h

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/*
 * Copyright (C) 2019 Inria
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef STMPE811_CONSTANTS_H
#define STMPE811_CONSTANTS_H
 
#include "stmpe811.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define STMPE811_I2C_ADDR_DEFAULT                   (0x41)      
#define STMPE811_CHIP_ID_VALUE                      (0x0811)    
/* @name    Registers
 * @{
 */
#define STMPE811_CHIP_ID                            (0x00)      
#define STMPE811_ID_VER                             (0x02)      
#define STMPE811_SYS_CTRL1                          (0x03)      
#define STMPE811_SYS_CTRL2                          (0x04)      
#define STMPE811_SPI_CFG                            (0x08)      
#define STMPE811_INT_CTRL                           (0x09)      
#define STMPE811_INT_EN                             (0x0A)      
#define STMPE811_INT_STA                            (0x0B)      
#define STMPE811_GPIO_EN                            (0x0C)      
#define STMPE811_GPIO_INT_STA                       (0x0D)      
#define STMPE811_ADC_INT_EN                         (0x0E)      
#define STMPE811_ADC_INT_STA                        (0x0F)      
#define STMPE811_GPIO_SET_PIN                       (0x10)      
#define STMPE811_GPIO_CLR_PIN                       (0x11)      
#define STMPE811_MP_STA                             (0x12)      
#define STMPE811_GPIO_DIR                           (0x13)      
#define STMPE811_GPIO_ED                            (0x14)      
#define STMPE811_GPIO_RE                            (0x15)      
#define STMPE811_GPIO_FE                            (0x16)      
#define STMPE811_GPIO_ALT_FUNCTION                  (0x17)      
#define STMPE811_ADC_CTRL1                          (0x20)      
#define STMPE811_ADC_CTRL2                          (0x21)      
#define STMPE811_ADC_CAPT                           (0x22)      
#define STMPE811_ADC_DATA_CHO                       (0x30)      
#define STMPE811_ADC_DATA_CH1                       (0x32)      
#define STMPE811_ADC_DATA_CH2                       (0x34)      
#define STMPE811_ADC_DATA_CH3                       (0x36)      
#define STMPE811_ADC_DATA_CH4                       (0x38)      
#define STMPE811_ADC_DATA_CH5                       (0x3A)      
#define STMPE811_ADC_DATA_CH6                       (0x3C)      
#define STMPE811_ADC_DATA_CH7                       (0x3E)      
#define STMPE811_TSC_CTRL                           (0x40)      
#define STMPE811_TSC_CFG                            (0x41)      
#define STMPE811_WDW_TR_X                           (0x42)      
#define STMPE811_WDW_TR_Y                           (0x44)      
#define STMPE811_WDW_BL_X                           (0x46)      
#define STMPE811_WDW_BL_Y                           (0x48)      
#define STMPE811_FIFO_TH                            (0x4A)      
#define STMPE811_FIFO_CTRL_STA                      (0x4B)      
#define STMPE811_FIFO_SIZE                          (0x4C)      
#define STMPE811_TSC_DATA_X                         (0x4D)      
#define STMPE811_TSC_DATA_Y                         (0x4F)      
#define STMPE811_TSC_DATA_Z                         (0x51)      
#define STMPE811_TSC_DATA_XYZ                       (0x52)      
#define STMPE811_TSC_DATA_INC                       (0x57)      
#define STMPE811_TSC_DATA_NON_INC                   (0xD7)      
#define STMPE811_TSC_FRACTION_Z                     (0x56)      
#define STMPE811_TSC_DATA                           (0x57)      
#define STMPE811_TSC_I_DRIVE                        (0x58)      
#define STMPE811_TSC_SHIELD                         (0x59)      
#define STMPE811_TEMP_CTRL                          (0x60)      
#define STMPE811_TEMP_DATA                          (0x61)      
#define STMPE811_TEMP_TH                            (0x62)      
/* @name    SYS_CTRL1 register bitfields
 * @{
 */
#define STMPE811_SYS_CTRL1_HIBERNATE                (1 << 0)    
#define STMPE811_SYS_CTRL1_SOFT_RESET               (1 << 1)    
/* @name    SYS_CTRL2 register bitfields
 * @{
 */
#define STMPE811_SYS_CTRL2_ADC_OFF                  (1 << 0)    
#define STMPE811_SYS_CTRL2_TSC_OFF                  (1 << 1)    
#define STMPE811_SYS_CTRL2_GPIO_OFF                 (1 << 2)    
#define STMPE811_SYS_CTRL2_TS_OFF                   (1 << 3)    
/* @name    INT_CTRL register bitfields
 * @{
 */
#define STMPE811_INT_CTRL_INT_POLARITY              (1 << 2)    
#define STMPE811_INT_CTRL_INT_TYPE                  (1 << 1)    
#define STMPE811_INT_CTRL_GLOBAL_INT                (1 << 0)    
/* @name    INT_EN register bitfields
 * @{
 */
#define STMPE811_INT_EN_TOUCH_DET                   (1 << 0)    
#define STMPE811_INT_EN_FIFO_TH                     (1 << 1)    
#define STMPE811_INT_EN_FIFO_OFLOW                  (1 << 2)    
#define STMPE811_INT_EN_FIFO_FULL                   (1 << 3)    
#define STMPE811_INT_EN_FIFO_EMPTY                  (1 << 4)    
#define STMPE811_INT_EN_TEMP_SENS                   (1 << 5)    
#define STMPE811_INT_EN_ADC                         (1 << 6)    
#define STMPE811_INT_EN_GPIO                        (1 << 7)    
/* @name    ADC_CTRL1 register bitfields
 * @{
 */
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_POS          (4)         
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_36           (0b000)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_44           (0b001)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_56           (0b010)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_64           (0b011)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_80           (0b100)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_96           (0b101)     
#define STMPE811_ADC_CTRL1_SAMPLE_TIME_124          (0b110)     
#define STMPE811_ADC_CTRL1_MOD_12B                  (1 << 3)    
/* @name    ADC_CTRL2 register bitfields
 * @{
 */
#define STMPE811_ADC_CTRL2_FREQ_1_625MHZ            (0b00)      
#define STMPE811_ADC_CTRL2_FREQ_3_25MHZ             (0b01)      
#define STMPE811_ADC_CTRL2_FREQ_6_5MHZ              (0b10)      
#define STMPE811_ADC_CTRL2_FREQ_6_5_2MHZ            (0b11)      
/* @name    TSC_CTRL register bitfields
 * @{
 */
#define STMPE811_TSC_CTRL_EN                        (1 << 0)    
#define STMPE811_TSC_CTRL_OPMOD_POS                 (1)         
#define STMPE811_TSC_CTRL_OPMOD_XYZ                 (0b000)     
#define STMPE811_TSC_CTRL_OPMOD_XY_ONLY             (0b001)     
#define STMPE811_TSC_CTRL_OPMOD_X_ONLY              (0b010)     
#define STMPE811_TSC_CTRL_OPMOD_Y_ONLY              (0b011)     
#define STMPE811_TSC_CTRL_OPMOD_Z_ONLY              (0b100)     
#define STMPE811_TSC_CTRL_TRACK_POS                 (4)         
#define STMPE811_TSC_CTRL_TRACK_NO                  (0b000)     
#define STMPE811_TSC_CTRL_TRACK_4                   (0b001)     
#define STMPE811_TSC_CTRL_TRACK_8                   (0b010)     
#define STMPE811_TSC_CTRL_TRACK_16                  (0b011)     
#define STMPE811_TSC_CTRL_TRACK_32                  (0b100)     
#define STMPE811_TSC_CTRL_TRACK_64                  (0b101)     
#define STMPE811_TSC_CTRL_TRACK_92                  (0b110)     
#define STMPE811_TSC_CTRL_TRACK_127                 (0b111)     
#define STMPE811_TSC_CTRL_STA                       (1 << 7)    
/* @name    TSC_CFG register bitfields
 * @{
 */
#define STMPE811_TSC_CFG_AVE_CTRL_POS               (6)         
#define STMPE811_TSC_CFG_AVE_CTRL_1                 (0b00)      
#define STMPE811_TSC_CFG_AVE_CTRL_2                 (0b01)      
#define STMPE811_TSC_CFG_AVE_CTRL_4                 (0b10)      
#define STMPE811_TSC_CFG_AVE_CTRL_8                 (0b11)      
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_POS        (3)         
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_10US       (0b000)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_50US       (0b001)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_100US      (0b010)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_500US      (0b011)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_1MS        (0b100)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_5MS        (0b101)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_10MS       (0b110)     
#define STMPE811_TSC_CFG_TOUCH_DET_DELAY_50MS       (0b111)     
#define STMPE811_TSC_CFG_SETTLING_10US              (0b000)     
#define STMPE811_TSC_CFG_SETTLING_100US             (0b001)     
#define STMPE811_TSC_CFG_SETTLING_500US             (0b010)     
#define STMPE811_TSC_CFG_SETTLING_1MS               (0b011)     
#define STMPE811_TSC_CFG_SETTLING_5MS               (0b100)     
#define STMPE811_TSC_CFG_SETTLING_10MS              (0b101)     
#define STMPE811_TSC_CFG_SETTLING_50MS              (0b110)     
#define STMPE811_TSC_CFG_SETTLING_100MS             (0b111)     
/* @name    FIFO_CTRL_STA register bitfields
 * @{
 */
#define STMPE811_FIFO_CTRL_STA_RESET                (1 << 0)    
/* @name    TSC_FRACTION_Z register bitfields
 * @{
 */
#define STMPE811_TSC_FRACTION_Z_0_8                 (0b000)     
#define STMPE811_TSC_FRACTION_Z_1_7                 (0b001)     
#define STMPE811_TSC_FRACTION_Z_2_6                 (0b010)     
#define STMPE811_TSC_FRACTION_Z_3_5                 (0b011)     
#define STMPE811_TSC_FRACTION_Z_4_4                 (0b100)     
#define STMPE811_TSC_FRACTION_Z_5_3                 (0b101)     
#define STMPE811_TSC_FRACTION_Z_6_2                 (0b110)     
#define STMPE811_TSC_FRACTION_Z_7_1                 (0b111)     
/* @name    TSC_I_DRIVE register bitfields
 * @{
 */
#define STMPE811_TSC_I_DRIVE_50MA                   (1 << 0)    
#ifdef __cplusplus
}
#endif
 
#endif /* STMPE811_CONSTANTS_H */