atmega_regs_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2016 INRIA
4  * 2017 Thomas Perrot <thomas.perrot@tupi.fr>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
24 #ifndef ATMEGA_REGS_COMMON_H
25 #define ATMEGA_REGS_COMMON_H
26 
27 #include <avr/io.h>
28 #include <avr/power.h>
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 #define REG8 volatile uint8_t
39 #define REG16 volatile uint16_t
40 
45 typedef struct {
52  REG16 OCR[3];
53 } mega_timer_t;
54 
58 typedef struct {
62  REG8 OCR[2];
63 } mini_timer_t;
64 
68 typedef struct {
72 #ifdef CPU_ATMEGA32U4
73  REG8 CSRD;
74 #else
76 #endif
78  REG8 DR;
79 } mega_uart_t;
80 
85 #if defined(TCCR0A)
86 #define MINI_TIMER0 ((mini_timer_t *)(uint16_t *)(&TCCR0A))
87 #define MINI_TIMER0_DIV TIMER_DIV1_8_64_128_1024
88 #endif
89 
90 #if defined(TCCR1A)
91 #define MEGA_TIMER1_BASE (uint16_t *)(&TCCR1A)
92 #define MEGA_TIMER1 ((mega_timer_t *)MEGA_TIMER1_BASE)
93 #endif
94 
95 #if defined(TCCR2A)
96 #define MINI_TIMER2 ((mini_timer_t *)(uint16_t *)(&TCCR2A))
97 #define MINI_TIMER2_DIV TIMER_DIV1_8_32_64_128_256_1024
98 #endif
99 
100 #if defined(TCCR3A)
101 #define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A)
102 #define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE)
103 #endif
104 
105 #if defined(TCCR4A)
106 #define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A)
107 #define MEGA_TIMER4 ((mega_timer_t *)MEGA_TIMER4_BASE)
108 #endif
109 
110 #if defined(TCCR5A)
111 #define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A)
112 #define MEGA_TIMER5 ((mega_timer_t *)MEGA_TIMER5_BASE)
113 #endif
114 
121 #if defined(UCSR0A)
122 #define MEGA_UART0_BASE ((uint16_t *)(&UCSR0A))
123 #define MEGA_UART0 ((mega_uart_t *)MEGA_UART0_BASE)
124 #endif
125 
126 #if defined(UCSR1A)
127 #define MEGA_UART1_BASE ((uint16_t *)(&UCSR1A))
128 #define MEGA_UART1 ((mega_uart_t *)MEGA_UART1_BASE)
129 #endif
130 
131 #if defined(UCSR2A)
132 #define MEGA_UART2_BASE ((uint16_t *)(&UCSR2A))
133 #define MEGA_UART2 ((mega_uart_t *)MEGA_UART2_BASE)
134 #endif
135 
136 #if defined(UCSR3A)
137 #define MEGA_UART3_BASE ((uint16_t *)(&UCSR3A))
138 #define MEGA_UART3 ((mega_uart_t *)MEGA_UART3_BASE)
139 #endif
140 
143 #ifdef __cplusplus
144 }
145 #endif
146 
147 #endif /* ATMEGA_REGS_COMMON_H */
148 
mini_timer_t::CRA
REG8 CRA
control A
Definition: atmega_regs_common.h:59
mini_timer_t::CNT
REG8 CNT
counter
Definition: atmega_regs_common.h:61
mega_uart_t
UART register map.
Definition: atmega_regs_common.h:68
mega_timer_t::ICR
REG16 ICR
input capture
Definition: atmega_regs_common.h:51
mega_uart_t::BRR
REG16 BRR
baud rate register
Definition: atmega_regs_common.h:77
REG8
#define REG8
Register types.
Definition: atmega_regs_common.h:38
mega_timer_t::CRB
REG8 CRB
control B
Definition: atmega_regs_common.h:47
mini_timer_t
8-bit timer register map
Definition: atmega_regs_common.h:58
mega_uart_t::CSRB
REG8 CSRB
control and status register B
Definition: atmega_regs_common.h:70
mega_uart_t::CSRA
REG8 CSRA
control and status register A
Definition: atmega_regs_common.h:69
mega_timer_t::reserved
REG8 reserved
reserved
Definition: atmega_regs_common.h:49
mega_timer_t
Timer register map.
Definition: atmega_regs_common.h:45
REG16
#define REG16
Shortcut to specify 16-bit wide registers.
Definition: msp430_regs.h:38
mega_uart_t::reserved
REG8 reserved
reserved
Definition: atmega_regs_common.h:75
mega_timer_t::CNT
REG16 CNT
counter
Definition: atmega_regs_common.h:50
mega_timer_t::CRA
REG8 CRA
control A
Definition: atmega_regs_common.h:46
mega_uart_t::DR
REG8 DR
data register
Definition: atmega_regs_common.h:78
mega_uart_t::CSRC
REG8 CSRC
control and status register C
Definition: atmega_regs_common.h:71
mini_timer_t::CRB
REG8 CRB
control B
Definition: atmega_regs_common.h:60
mega_timer_t::CRC
REG8 CRC
control C
Definition: atmega_regs_common.h:48