cc2538.h

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/*
 * Copyright (C) 2014 Loci Controls Inc.
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef CC2538_H
#define CC2538_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ************************************************************************** */
/*   CMSIS DEFINITIONS FOR CC2538 */
/* ************************************************************************** */
 
typedef enum IRQn
{
    /******  Cortex-M3 Processor Exceptions Numbers ****************************/
    ResetHandler_IRQn     = -15, 
    NonMaskableInt_IRQn   = -14, 
    HardFault_IRQn        = -13, 
    MemoryManagement_IRQn = -12, 
    BusFault_IRQn         = -11, 
    UsageFault_IRQn       = -10, 
    SVCall_IRQn           = - 5, 
    DebugMonitor_IRQn     = - 4, 
    PendSV_IRQn           = - 2, 
    SysTick_IRQn          = - 1, 
    /******  CC2538 specific Interrupt Numbers *********************************/
    GPIO_PORT_A_IRQn      =   0, 
    GPIO_PORT_B_IRQn      =   1, 
    GPIO_PORT_C_IRQn      =   2, 
    GPIO_PORT_D_IRQn      =   3, 
    UART0_IRQn            =   5, 
    UART1_IRQn            =   6, 
    SSI0_IRQn             =   7, 
    I2C_IRQn              =   8, 
    ADC_IRQn              =  14, 
    WDT_IRQn              =  18, 
    GPTIMER_0A_IRQn       =  19, 
    GPTIMER_0B_IRQn       =  20, 
    GPTIMER_1A_IRQn       =  21, 
    GPTIMER_1B_IRQn       =  22, 
    GPTIMER_2A_IRQn       =  23, 
    GPTIMER_2B_IRQn       =  24, 
    ADC_CMP_IRQn          =  25, 
    RF_RXTX_ALT_IRQn      =  26, 
    RF_ERR_ALT_IRQn       =  27, 
    SYS_CTRL_IRQn         =  28, 
    FLASH_CTRL_IRQn       =  29, 
    AES_ALT_IRQn          =  30, 
    PKA_ALT_IRQn          =  31, 
    SM_TIMER_ALT_IRQn     =  32, 
    MAC_TIMER_ALT_IRQn    =  33, 
    SSI1_IRQn             =  34, 
    GPTIMER_3A_IRQn       =  35, 
    GPTIMER_3B_IRQn       =  36, 
    UDMA_IRQn             =  46, 
    UDMA_ERR_IRQn         =  47, 
    USB_IRQn              = 140, 
    RF_RXTX_IRQn          = 141, 
    RF_ERR_IRQn           = 142, 
    AES_IRQn              = 143, 
    PKA_IRQn              = 144, 
    SM_TIMER_IRQn         = 145, 
    MACTIMER_IRQn         = 146, 
    PERIPH_COUNT_IRQn     = (MACTIMER_IRQn + 1) 
} IRQn_Type;
 
void Reset_Handler(void);        
void NMI_Handler(void);          
void HardFault_Handler(void);    
void MemManage_Handler(void);    
void BusFault_Handler(void);     
void UsageFault_Handler(void);   
void SVC_Handler(void);          
void DebugMon_Handler(void);     
void PendSV_Handler(void);       
void SysTick_Handler(void);      
#define __CM3_REV              0x0200 
#define __MPU_PRESENT          1      
#define __NVIC_PRIO_BITS       3      
#define __Vendor_SysTickConfig 0      
#include <core_cm3.h>
 
#define IEEE_ADDR_MSWORD            ( *(const uint32_t*)0x00280028 ) 
#define IEEE_ADDR_LSWORD            ( *(const uint32_t*)0x0028002c ) 
typedef volatile uint32_t cc2538_reg_t; 
#define FLASH_BASE                  0x00200000 
#define SRAM_BASE                   0x20000000 
#define PERIPH_BASE                 0x40000000 
#define SRAM_BB_BASE                0x22000000 
#define SSI0_CR0                    ( *(cc2538_reg_t*)0x40008000 ) 
#define SSI0_CR1                    ( *(cc2538_reg_t*)0x40008004 ) 
#define SSI0_DR                     ( *(cc2538_reg_t*)0x40008008 ) 
#define SSI0_SR                     ( *(cc2538_reg_t*)0x4000800c ) 
#define SSI0_CPSR                   ( *(cc2538_reg_t*)0x40008010 ) 
#define SSI0_IM                     ( *(cc2538_reg_t*)0x40008014 ) 
#define SSI0_RIS                    ( *(cc2538_reg_t*)0x40008018 ) 
#define SSI0_MIS                    ( *(cc2538_reg_t*)0x4000801c ) 
#define SSI0_ICR                    ( *(cc2538_reg_t*)0x40008020 ) 
#define SSI0_DMACTL                 ( *(cc2538_reg_t*)0x40008024 ) 
#define SSI0_CC                     ( *(cc2538_reg_t*)0x40008fc8 ) 
#define SSI1_CR0                    ( *(cc2538_reg_t*)0x40009000 ) 
#define SSI1_CR1                    ( *(cc2538_reg_t*)0x40009004 ) 
#define SSI1_DR                     ( *(cc2538_reg_t*)0x40009008 ) 
#define SSI1_SR                     ( *(cc2538_reg_t*)0x4000900c ) 
#define SSI1_CPSR                   ( *(cc2538_reg_t*)0x40009010 ) 
#define SSI1_IM                     ( *(cc2538_reg_t*)0x40009014 ) 
#define SSI1_RIS                    ( *(cc2538_reg_t*)0x40009018 ) 
#define SSI1_MIS                    ( *(cc2538_reg_t*)0x4000901c ) 
#define SSI1_ICR                    ( *(cc2538_reg_t*)0x40009020 ) 
#define SSI1_DMACTL                 ( *(cc2538_reg_t*)0x40009024 ) 
#define SSI1_CC                     ( *(cc2538_reg_t*)0x40009fc8 ) 
#define UART0_DR                    ( *(cc2538_reg_t*)0x4000c000 ) 
#define UART0_ECR                   ( *(cc2538_reg_t*)0x4000c004 ) 
#define UART0_RSR                   ( *(cc2538_reg_t*)0x4000c004 ) 
#define UART0_FR                    ( *(cc2538_reg_t*)0x4000c018 ) 
#define UART0_ILPR                  ( *(cc2538_reg_t*)0x4000c020 ) 
#define UART0_IBRD                  ( *(cc2538_reg_t*)0x4000c024 ) 
#define UART0_FBRD                  ( *(cc2538_reg_t*)0x4000c028 ) 
#define UART0_LCRH                  ( *(cc2538_reg_t*)0x4000c02c ) 
#define UART0_CTL                   ( *(cc2538_reg_t*)0x4000c030 ) 
#define UART0_IFLS                  ( *(cc2538_reg_t*)0x4000c034 ) 
#define UART0_IM                    ( *(cc2538_reg_t*)0x4000c038 ) 
#define UART0_RIS                   ( *(cc2538_reg_t*)0x4000c03c ) 
#define UART0_MIS                   ( *(cc2538_reg_t*)0x4000c040 ) 
#define UART0_ICR                   ( *(cc2538_reg_t*)0x4000c044 ) 
#define UART0_DMACTL                ( *(cc2538_reg_t*)0x4000c048 ) 
#define UART0_LCTL                  ( *(cc2538_reg_t*)0x4000c090 ) 
#define UART0_LSS                   ( *(cc2538_reg_t*)0x4000c094 ) 
#define UART0_LTIM                  ( *(cc2538_reg_t*)0x4000c098 ) 
#define UART0_NINEBITADDR           ( *(cc2538_reg_t*)0x4000c0a4 ) 
#define UART0_NINEBITAMASK          ( *(cc2538_reg_t*)0x4000c0a8 ) 
#define UART0_PP                    ( *(cc2538_reg_t*)0x4000cfc0 ) 
#define UART0_CC                    ( *(cc2538_reg_t*)0x4000cfc8 ) 
#define UART1_DR                    ( *(cc2538_reg_t*)0x4000d000 ) 
#define UART1_ECR                   ( *(cc2538_reg_t*)0x4000d004 ) 
#define UART1_RSR                   ( *(cc2538_reg_t*)0x4000d004 ) 
#define UART1_FR                    ( *(cc2538_reg_t*)0x4000d018 ) 
#define UART1_ILPR                  ( *(cc2538_reg_t*)0x4000d020 ) 
#define UART1_IBRD                  ( *(cc2538_reg_t*)0x4000d024 ) 
#define UART1_FBRD                  ( *(cc2538_reg_t*)0x4000d028 ) 
#define UART1_LCRH                  ( *(cc2538_reg_t*)0x4000d02c ) 
#define UART1_CTL                   ( *(cc2538_reg_t*)0x4000d030 ) 
#define UART1_IFLS                  ( *(cc2538_reg_t*)0x4000d034 ) 
#define UART1_IM                    ( *(cc2538_reg_t*)0x4000d038 ) 
#define UART1_RIS                   ( *(cc2538_reg_t*)0x4000d03c ) 
#define UART1_MIS                   ( *(cc2538_reg_t*)0x4000d040 ) 
#define UART1_ICR                   ( *(cc2538_reg_t*)0x4000d044 ) 
#define UART1_DMACTL                ( *(cc2538_reg_t*)0x4000d048 ) 
#define UART1_LCTL                  ( *(cc2538_reg_t*)0x4000d090 ) 
#define UART1_LSS                   ( *(cc2538_reg_t*)0x4000d094 ) 
#define UART1_LTIM                  ( *(cc2538_reg_t*)0x4000d098 ) 
#define UART1_NINEBITADDR           ( *(cc2538_reg_t*)0x4000d0a4 ) 
#define UART1_NINEBITAMASK          ( *(cc2538_reg_t*)0x4000d0a8 ) 
#define UART1_PP                    ( *(cc2538_reg_t*)0x4000dfc0 ) 
#define UART1_CC                    ( *(cc2538_reg_t*)0x4000dfc8 ) 
#define I2CM_SA                     ( *(cc2538_reg_t*)0x40020000 ) 
#define I2CM_CTRL                   ( *(cc2538_reg_t*)0x40020004 ) 
#define I2CM_STAT                   ( *(cc2538_reg_t*)0x40020004 ) 
#define I2CM_DR                     ( *(cc2538_reg_t*)0x40020008 ) 
#define I2CM_TPR                    ( *(cc2538_reg_t*)0x4002000c ) 
#define I2CM_IMR                    ( *(cc2538_reg_t*)0x40020010 ) 
#define I2CM_RIS                    ( *(cc2538_reg_t*)0x40020014 ) 
#define I2CM_MIS                    ( *(cc2538_reg_t*)0x40020018 ) 
#define I2CM_ICR                    ( *(cc2538_reg_t*)0x4002001c ) 
#define I2CM_CR                     ( *(cc2538_reg_t*)0x40020020 ) 
#define I2CS_OAR                    ( *(cc2538_reg_t*)0x40020800 ) 
#define I2CS_CTRL                   ( *(cc2538_reg_t*)0x40020804 ) 
#define I2CS_STAT                   ( *(cc2538_reg_t*)0x40020804 ) 
#define I2CS_DR                     ( *(cc2538_reg_t*)0x40020808 ) 
#define I2CS_IMR                    ( *(cc2538_reg_t*)0x4002080c ) 
#define I2CS_RIS                    ( *(cc2538_reg_t*)0x40020810 ) 
#define I2CS_MIS                    ( *(cc2538_reg_t*)0x40020814 ) 
#define I2CS_ICR                    ( *(cc2538_reg_t*)0x40020818 ) 
#define GPTIMER0_CFG                ( *(cc2538_reg_t*)0x40030000 ) 
#define GPTIMER0_TAMR               ( *(cc2538_reg_t*)0x40030004 ) 
#define GPTIMER0_TBMR               ( *(cc2538_reg_t*)0x40030008 ) 
#define GPTIMER0_CTL                ( *(cc2538_reg_t*)0x4003000c ) 
#define GPTIMER0_SYNC               ( *(cc2538_reg_t*)0x40030010 ) 
#define GPTIMER0_IMR                ( *(cc2538_reg_t*)0x40030018 ) 
#define GPTIMER0_RIS                ( *(cc2538_reg_t*)0x4003001c ) 
#define GPTIMER0_MIS                ( *(cc2538_reg_t*)0x40030020 ) 
#define GPTIMER0_ICR                ( *(cc2538_reg_t*)0x40030024 ) 
#define GPTIMER0_TAILR              ( *(cc2538_reg_t*)0x40030028 ) 
#define GPTIMER0_TBILR              ( *(cc2538_reg_t*)0x4003002c ) 
#define GPTIMER0_TAMATCHR           ( *(cc2538_reg_t*)0x40030030 ) 
#define GPTIMER0_TBMATCHR           ( *(cc2538_reg_t*)0x40030034 ) 
#define GPTIMER0_TAPR               ( *(cc2538_reg_t*)0x40030038 ) 
#define GPTIMER0_TBPR               ( *(cc2538_reg_t*)0x4003003c ) 
#define GPTIMER0_TAPMR              ( *(cc2538_reg_t*)0x40030040 ) 
#define GPTIMER0_TBPMR              ( *(cc2538_reg_t*)0x40030044 ) 
#define GPTIMER0_TAR                ( *(cc2538_reg_t*)0x40030048 ) 
#define GPTIMER0_TBR                ( *(cc2538_reg_t*)0x4003004c ) 
#define GPTIMER0_TAV                ( *(cc2538_reg_t*)0x40030050 ) 
#define GPTIMER0_TBV                ( *(cc2538_reg_t*)0x40030054 ) 
#define GPTIMER0_TAPS               ( *(cc2538_reg_t*)0x4003005c ) 
#define GPTIMER0_TBPS               ( *(cc2538_reg_t*)0x40030060 ) 
#define GPTIMER0_TAPV               ( *(cc2538_reg_t*)0x40030064 ) 
#define GPTIMER0_TBPV               ( *(cc2538_reg_t*)0x40030068 ) 
#define GPTIMER0_PP                 ( *(cc2538_reg_t*)0x40030fc0 ) 
#define GPTIMER1_CFG                ( *(cc2538_reg_t*)0x40031000 ) 
#define GPTIMER1_TAMR               ( *(cc2538_reg_t*)0x40031004 ) 
#define GPTIMER1_TBMR               ( *(cc2538_reg_t*)0x40031008 ) 
#define GPTIMER1_CTL                ( *(cc2538_reg_t*)0x4003100c ) 
#define GPTIMER1_SYNC               ( *(cc2538_reg_t*)0x40031010 ) 
#define GPTIMER1_IMR                ( *(cc2538_reg_t*)0x40031018 ) 
#define GPTIMER1_RIS                ( *(cc2538_reg_t*)0x4003101c ) 
#define GPTIMER1_MIS                ( *(cc2538_reg_t*)0x40031020 ) 
#define GPTIMER1_ICR                ( *(cc2538_reg_t*)0x40031024 ) 
#define GPTIMER1_TAILR              ( *(cc2538_reg_t*)0x40031028 ) 
#define GPTIMER1_TBILR              ( *(cc2538_reg_t*)0x4003102c ) 
#define GPTIMER1_TAMATCHR           ( *(cc2538_reg_t*)0x40031030 ) 
#define GPTIMER1_TBMATCHR           ( *(cc2538_reg_t*)0x40031034 ) 
#define GPTIMER1_TAPR               ( *(cc2538_reg_t*)0x40031038 ) 
#define GPTIMER1_TBPR               ( *(cc2538_reg_t*)0x4003103c ) 
#define GPTIMER1_TAPMR              ( *(cc2538_reg_t*)0x40031040 ) 
#define GPTIMER1_TBPMR              ( *(cc2538_reg_t*)0x40031044 ) 
#define GPTIMER1_TAR                ( *(cc2538_reg_t*)0x40031048 ) 
#define GPTIMER1_TBR                ( *(cc2538_reg_t*)0x4003104c ) 
#define GPTIMER1_TAV                ( *(cc2538_reg_t*)0x40031050 ) 
#define GPTIMER1_TBV                ( *(cc2538_reg_t*)0x40031054 ) 
#define GPTIMER1_TAPS               ( *(cc2538_reg_t*)0x4003105c ) 
#define GPTIMER1_TBPS               ( *(cc2538_reg_t*)0x40031060 ) 
#define GPTIMER1_TAPV               ( *(cc2538_reg_t*)0x40031064 ) 
#define GPTIMER1_TBPV               ( *(cc2538_reg_t*)0x40031068 ) 
#define GPTIMER1_PP                 ( *(cc2538_reg_t*)0x40031fc0 ) 
#define GPTIMER2_CFG                ( *(cc2538_reg_t*)0x40032000 ) 
#define GPTIMER2_TAMR               ( *(cc2538_reg_t*)0x40032004 ) 
#define GPTIMER2_TBMR               ( *(cc2538_reg_t*)0x40032008 ) 
#define GPTIMER2_CTL                ( *(cc2538_reg_t*)0x4003200c ) 
#define GPTIMER2_SYNC               ( *(cc2538_reg_t*)0x40032010 ) 
#define GPTIMER2_IMR                ( *(cc2538_reg_t*)0x40032018 ) 
#define GPTIMER2_RIS                ( *(cc2538_reg_t*)0x4003201c ) 
#define GPTIMER2_MIS                ( *(cc2538_reg_t*)0x40032020 ) 
#define GPTIMER2_ICR                ( *(cc2538_reg_t*)0x40032024 ) 
#define GPTIMER2_TAILR              ( *(cc2538_reg_t*)0x40032028 ) 
#define GPTIMER2_TBILR              ( *(cc2538_reg_t*)0x4003202c ) 
#define GPTIMER2_TAMATCHR           ( *(cc2538_reg_t*)0x40032030 ) 
#define GPTIMER2_TBMATCHR           ( *(cc2538_reg_t*)0x40032034 ) 
#define GPTIMER2_TAPR               ( *(cc2538_reg_t*)0x40032038 ) 
#define GPTIMER2_TBPR               ( *(cc2538_reg_t*)0x4003203c ) 
#define GPTIMER2_TAPMR              ( *(cc2538_reg_t*)0x40032040 ) 
#define GPTIMER2_TBPMR              ( *(cc2538_reg_t*)0x40032044 ) 
#define GPTIMER2_TAR                ( *(cc2538_reg_t*)0x40032048 ) 
#define GPTIMER2_TBR                ( *(cc2538_reg_t*)0x4003204c ) 
#define GPTIMER2_TAV                ( *(cc2538_reg_t*)0x40032050 ) 
#define GPTIMER2_TBV                ( *(cc2538_reg_t*)0x40032054 ) 
#define GPTIMER2_TAPS               ( *(cc2538_reg_t*)0x4003205c ) 
#define GPTIMER2_TBPS               ( *(cc2538_reg_t*)0x40032060 ) 
#define GPTIMER2_TAPV               ( *(cc2538_reg_t*)0x40032064 ) 
#define GPTIMER2_TBPV               ( *(cc2538_reg_t*)0x40032068 ) 
#define GPTIMER2_PP                 ( *(cc2538_reg_t*)0x40032fc0 ) 
#define GPTIMER3_CFG                ( *(cc2538_reg_t*)0x40033000 ) 
#define GPTIMER3_TAMR               ( *(cc2538_reg_t*)0x40033004 ) 
#define GPTIMER3_TBMR               ( *(cc2538_reg_t*)0x40033008 ) 
#define GPTIMER3_CTL                ( *(cc2538_reg_t*)0x4003300c ) 
#define GPTIMER3_SYNC               ( *(cc2538_reg_t*)0x40033010 ) 
#define GPTIMER3_IMR                ( *(cc2538_reg_t*)0x40033018 ) 
#define GPTIMER3_RIS                ( *(cc2538_reg_t*)0x4003301c ) 
#define GPTIMER3_MIS                ( *(cc2538_reg_t*)0x40033020 ) 
#define GPTIMER3_ICR                ( *(cc2538_reg_t*)0x40033024 ) 
#define GPTIMER3_TAILR              ( *(cc2538_reg_t*)0x40033028 ) 
#define GPTIMER3_TBILR              ( *(cc2538_reg_t*)0x4003302c ) 
#define GPTIMER3_TAMATCHR           ( *(cc2538_reg_t*)0x40033030 ) 
#define GPTIMER3_TBMATCHR           ( *(cc2538_reg_t*)0x40033034 ) 
#define GPTIMER3_TAPR               ( *(cc2538_reg_t*)0x40033038 ) 
#define GPTIMER3_TBPR               ( *(cc2538_reg_t*)0x4003303c ) 
#define GPTIMER3_TAPMR              ( *(cc2538_reg_t*)0x40033040 ) 
#define GPTIMER3_TBPMR              ( *(cc2538_reg_t*)0x40033044 ) 
#define GPTIMER3_TAR                ( *(cc2538_reg_t*)0x40033048 ) 
#define GPTIMER3_TBR                ( *(cc2538_reg_t*)0x4003304c ) 
#define GPTIMER3_TAV                ( *(cc2538_reg_t*)0x40033050 ) 
#define GPTIMER3_TBV                ( *(cc2538_reg_t*)0x40033054 ) 
#define GPTIMER3_TAPS               ( *(cc2538_reg_t*)0x4003305c ) 
#define GPTIMER3_TBPS               ( *(cc2538_reg_t*)0x40033060 ) 
#define GPTIMER3_TAPV               ( *(cc2538_reg_t*)0x40033064 ) 
#define GPTIMER3_TBPV               ( *(cc2538_reg_t*)0x40033068 ) 
#define GPTIMER3_PP                 ( *(cc2538_reg_t*)0x40033fc0 ) 
#define RFCORE_FFSM_SRCRESMASK0     ( *(cc2538_reg_t*)0x40088580 ) 
#define RFCORE_FFSM_SRCRESMASK1     ( *(cc2538_reg_t*)0x40088584 ) 
#define RFCORE_FFSM_SRCRESMASK2     ( *(cc2538_reg_t*)0x40088588 ) 
#define RFCORE_FFSM_SRCRESINDEX     ( *(cc2538_reg_t*)0x4008858c ) 
#define RFCORE_FFSM_SRCEXTPENDEN0   ( *(cc2538_reg_t*)0x40088590 ) 
#define RFCORE_FFSM_SRCEXTPENDEN1   ( *(cc2538_reg_t*)0x40088594 ) 
#define RFCORE_FFSM_SRCEXTPENDEN2   ( *(cc2538_reg_t*)0x40088598 ) 
#define RFCORE_FFSM_SRCSHORTPENDEN0 ( *(cc2538_reg_t*)0x4008859c ) 
#define RFCORE_FFSM_SRCSHORTPENDEN1 ( *(cc2538_reg_t*)0x400885a0 ) 
#define RFCORE_FFSM_SRCSHORTPENDEN2 ( *(cc2538_reg_t*)0x400885a4 ) 
#define RFCORE_FFSM_EXT_ADDR0       ( *(cc2538_reg_t*)0x400885a8 ) 
#define RFCORE_FFSM_EXT_ADDR1       ( *(cc2538_reg_t*)0x400885ac ) 
#define RFCORE_FFSM_EXT_ADDR2       ( *(cc2538_reg_t*)0x400885b0 ) 
#define RFCORE_FFSM_EXT_ADDR3       ( *(cc2538_reg_t*)0x400885b4 ) 
#define RFCORE_FFSM_EXT_ADDR4       ( *(cc2538_reg_t*)0x400885b8 ) 
#define RFCORE_FFSM_EXT_ADDR5       ( *(cc2538_reg_t*)0x400885bc ) 
#define RFCORE_FFSM_EXT_ADDR6       ( *(cc2538_reg_t*)0x400885c0 ) 
#define RFCORE_FFSM_EXT_ADDR7       ( *(cc2538_reg_t*)0x400885c4 ) 
#define RFCORE_FFSM_PAN_ID0         ( *(cc2538_reg_t*)0x400885c8 ) 
#define RFCORE_FFSM_PAN_ID1         ( *(cc2538_reg_t*)0x400885cc ) 
#define RFCORE_FFSM_SHORT_ADDR0     ( *(cc2538_reg_t*)0x400885d0 ) 
#define RFCORE_FFSM_SHORT_ADDR1     ( *(cc2538_reg_t*)0x400885d4 ) 
#define RFCORE_XREG_FRMFILT0        ( *(cc2538_reg_t*)0x40088600 ) 
#define RFCORE_XREG_FRMFILT1        ( *(cc2538_reg_t*)0x40088604 ) 
#define RFCORE_XREG_SRCMATCH        ( *(cc2538_reg_t*)0x40088608 ) 
#define RFCORE_XREG_SRCSHORTEN0     ( *(cc2538_reg_t*)0x4008860c ) 
#define RFCORE_XREG_SRCSHORTEN1     ( *(cc2538_reg_t*)0x40088610 ) 
#define RFCORE_XREG_SRCSHORTEN2     ( *(cc2538_reg_t*)0x40088614 ) 
#define RFCORE_XREG_SRCEXTEN0       ( *(cc2538_reg_t*)0x40088618 ) 
#define RFCORE_XREG_SRCEXTEN1       ( *(cc2538_reg_t*)0x4008861c ) 
#define RFCORE_XREG_SRCEXTEN2       ( *(cc2538_reg_t*)0x40088620 ) 
#define RFCORE_XREG_FRMCTRL0        ( *(cc2538_reg_t*)0x40088624 ) 
#define RFCORE_XREG_FRMCTRL1        ( *(cc2538_reg_t*)0x40088628 ) 
#define RFCORE_XREG_RXENABLE        ( *(cc2538_reg_t*)0x4008862c ) 
#define RFCORE_XREG_RXMASKSET       ( *(cc2538_reg_t*)0x40088630 ) 
#define RFCORE_XREG_RXMASKCLR       ( *(cc2538_reg_t*)0x40088634 ) 
#define RFCORE_XREG_FREQTUNE        ( *(cc2538_reg_t*)0x40088638 ) 
#define RFCORE_XREG_FREQCTRL        ( *(cc2538_reg_t*)0x4008863c ) 
#define RFCORE_XREG_TXPOWER         ( *(cc2538_reg_t*)0x40088640 ) 
#define RFCORE_XREG_TXCTRL          ( *(cc2538_reg_t*)0x40088644 ) 
#define RFCORE_XREG_FSMSTAT0        ( *(cc2538_reg_t*)0x40088648 ) 
#define RFCORE_XREG_FSMSTAT1        ( *(cc2538_reg_t*)0x4008864c ) 
#define RFCORE_XREG_FIFOPCTRL       ( *(cc2538_reg_t*)0x40088650 ) 
#define RFCORE_XREG_FSMCTRL         ( *(cc2538_reg_t*)0x40088654 ) 
#define RFCORE_XREG_CCACTRL0        ( *(cc2538_reg_t*)0x40088658 ) 
#define RFCORE_XREG_CCACTRL1        ( *(cc2538_reg_t*)0x4008865c ) 
#define RFCORE_XREG_RSSI            ( *(cc2538_reg_t*)0x40088660 ) 
#define RFCORE_XREG_RSSISTAT        ( *(cc2538_reg_t*)0x40088664 ) 
#define RFCORE_XREG_RXFIRST         ( *(cc2538_reg_t*)0x40088668 ) 
#define RFCORE_XREG_RXFIFOCNT       ( *(cc2538_reg_t*)0x4008866c ) 
#define RFCORE_XREG_TXFIFOCNT       ( *(cc2538_reg_t*)0x40088670 ) 
#define RFCORE_XREG_RXFIRST_PTR     ( *(cc2538_reg_t*)0x40088674 ) 
#define RFCORE_XREG_RXLAST_PTR      ( *(cc2538_reg_t*)0x40088678 ) 
#define RFCORE_XREG_RXP1_PTR        ( *(cc2538_reg_t*)0x4008867c ) 
#define RFCORE_XREG_TXFIRST_PTR     ( *(cc2538_reg_t*)0x40088684 ) 
#define RFCORE_XREG_TXLAST_PTR      ( *(cc2538_reg_t*)0x40088688 ) 
#define RFCORE_XREG_RFIRQM0         ( *(cc2538_reg_t*)0x4008868c ) 
#define RFCORE_XREG_RFIRQM1         ( *(cc2538_reg_t*)0x40088690 ) 
#define RFCORE_XREG_RFERRM          ( *(cc2538_reg_t*)0x40088694 ) 
#define RFCORE_XREG_RFRND           ( *(cc2538_reg_t*)0x4008869c ) 
#define RFCORE_XREG_MDMCTRL0        ( *(cc2538_reg_t*)0x400886a0 ) 
#define RFCORE_XREG_MDMCTRL1        ( *(cc2538_reg_t*)0x400886a4 ) 
#define RFCORE_XREG_FREQEST         ( *(cc2538_reg_t*)0x400886a8 ) 
#define RFCORE_XREG_RXCTRL          ( *(cc2538_reg_t*)0x400886ac ) 
#define RFCORE_XREG_FSCTRL          ( *(cc2538_reg_t*)0x400886b0 ) 
#define RFCORE_XREG_FSCAL0          ( *(cc2538_reg_t*)0x400886b4 ) 
#define RFCORE_XREG_FSCAL1          ( *(cc2538_reg_t*)0x400886b8 ) 
#define RFCORE_XREG_FSCAL2          ( *(cc2538_reg_t*)0x400886bc ) 
#define RFCORE_XREG_FSCAL3          ( *(cc2538_reg_t*)0x400886c0 ) 
#define RFCORE_XREG_AGCCTRL0        ( *(cc2538_reg_t*)0x400886c4 ) 
#define RFCORE_XREG_AGCCTRL1        ( *(cc2538_reg_t*)0x400886c8 ) 
#define RFCORE_XREG_AGCCTRL2        ( *(cc2538_reg_t*)0x400886cc ) 
#define RFCORE_XREG_AGCCTRL3        ( *(cc2538_reg_t*)0x400886d0 ) 
#define RFCORE_XREG_ADCTEST0        ( *(cc2538_reg_t*)0x400886d4 ) 
#define RFCORE_XREG_ADCTEST1        ( *(cc2538_reg_t*)0x400886d8 ) 
#define RFCORE_XREG_ADCTEST2        ( *(cc2538_reg_t*)0x400886dc ) 
#define RFCORE_XREG_MDMTEST0        ( *(cc2538_reg_t*)0x400886e0 ) 
#define RFCORE_XREG_MDMTEST1        ( *(cc2538_reg_t*)0x400886e4 ) 
#define RFCORE_XREG_DACTEST0        ( *(cc2538_reg_t*)0x400886e8 ) 
#define RFCORE_XREG_DACTEST1        ( *(cc2538_reg_t*)0x400886ec ) 
#define RFCORE_XREG_DACTEST2        ( *(cc2538_reg_t*)0x400886f0 ) 
#define RFCORE_XREG_ATEST           ( *(cc2538_reg_t*)0x400886f4 ) 
#define RFCORE_XREG_PTEST0          ( *(cc2538_reg_t*)0x400886f8 ) 
#define RFCORE_XREG_PTEST1          ( *(cc2538_reg_t*)0x400886fc ) 
#define RFCORE_XREG_CSPCTRL         ( *(cc2538_reg_t*)0x40088780 ) 
#define RFCORE_XREG_CSPSTAT         ( *(cc2538_reg_t*)0x40088784 ) 
#define RFCORE_XREG_CSPX            ( *(cc2538_reg_t*)0x40088788 ) 
#define RFCORE_XREG_CSPY            ( *(cc2538_reg_t*)0x4008878c ) 
#define RFCORE_XREG_CSPZ            ( *(cc2538_reg_t*)0x40088790 ) 
#define RFCORE_XREG_CSPT            ( *(cc2538_reg_t*)0x40088794 ) 
#define RFCORE_XREG_RFC_OBS_CTRL0   ( *(cc2538_reg_t*)0x400887ac ) 
#define RFCORE_XREG_RFC_OBS_CTRL1   ( *(cc2538_reg_t*)0x400887b0 ) 
#define RFCORE_XREG_RFC_OBS_CTRL2   ( *(cc2538_reg_t*)0x400887b4 ) 
#define RFCORE_XREG_TXFILTCFG       ( *(cc2538_reg_t*)0x400887e8 ) 
#define RFCORE_SFR_MTCSPCFG         ( *(cc2538_reg_t*)0x40088800 ) 
#define RFCORE_SFR_MTCTRL           ( *(cc2538_reg_t*)0x40088804 ) 
#define RFCORE_SFR_MTIRQM           ( *(cc2538_reg_t*)0x40088808 ) 
#define RFCORE_SFR_MTIRQF           ( *(cc2538_reg_t*)0x4008880c ) 
#define RFCORE_SFR_MTMSEL           ( *(cc2538_reg_t*)0x40088810 ) 
#define RFCORE_SFR_MTM0             ( *(cc2538_reg_t*)0x40088814 ) 
#define RFCORE_SFR_MTM1             ( *(cc2538_reg_t*)0x40088818 ) 
#define RFCORE_SFR_MTMOVF2          ( *(cc2538_reg_t*)0x4008881c ) 
#define RFCORE_SFR_MTMOVF1          ( *(cc2538_reg_t*)0x40088820 ) 
#define RFCORE_SFR_MTMOVF0          ( *(cc2538_reg_t*)0x40088824 ) 
#define RFCORE_SFR_RFDATA           ( *(cc2538_reg_t*)0x40088828 ) 
#define RFCORE_SFR_RFERRF           ( *(cc2538_reg_t*)0x4008882c ) 
#define RFCORE_SFR_RFIRQF1          ( *(cc2538_reg_t*)0x40088830 ) 
#define RFCORE_SFR_RFIRQF0          ( *(cc2538_reg_t*)0x40088834 ) 
#define RFCORE_SFR_RFST             ( *(cc2538_reg_t*)0x40088838 ) 
#define USB_ADDR                    ( *(cc2538_reg_t*)0x40089000 ) 
#define USB_POW                     ( *(cc2538_reg_t*)0x40089004 ) 
#define USB_IIF                     ( *(cc2538_reg_t*)0x40089008 ) 
#define USB_OIF                     ( *(cc2538_reg_t*)0x40089010 ) 
#define USB_CIF                     ( *(cc2538_reg_t*)0x40089018 ) 
#define USB_IIE                     ( *(cc2538_reg_t*)0x4008901c ) 
#define USB_OIE                     ( *(cc2538_reg_t*)0x40089024 ) 
#define USB_CIE                     ( *(cc2538_reg_t*)0x4008902c ) 
#define USB_FRML                    ( *(cc2538_reg_t*)0x40089030 ) 
#define USB_FRMH                    ( *(cc2538_reg_t*)0x40089034 ) 
#define USB_INDEX                   ( *(cc2538_reg_t*)0x40089038 ) 
#define USB_CTRL                    ( *(cc2538_reg_t*)0x4008903c ) 
#define USB_MAXI                    ( *(cc2538_reg_t*)0x40089040 ) 
#define USB_CS0_CSIL                ( *(cc2538_reg_t*)0x40089044 ) 
#define USB_CSIH                    ( *(cc2538_reg_t*)0x40089048 ) 
#define USB_MAXO                    ( *(cc2538_reg_t*)0x4008904c ) 
#define USB_CSOL                    ( *(cc2538_reg_t*)0x40089050 ) 
#define USB_CSOH                    ( *(cc2538_reg_t*)0x40089054 ) 
#define USB_CNT0_CNTL               ( *(cc2538_reg_t*)0x40089058 ) 
#define USB_CNTH                    ( *(cc2538_reg_t*)0x4008905c ) 
#define USB_F0                      ( *(cc2538_reg_t*)0x40089080 ) 
#define USB_F1                      ( *(cc2538_reg_t*)0x40089088 ) 
#define USB_F2                      ( *(cc2538_reg_t*)0x40089090 ) 
#define USB_F3                      ( *(cc2538_reg_t*)0x40089098 ) 
#define USB_F4                      ( *(cc2538_reg_t*)0x400890a0 ) 
#define USB_F5                      ( *(cc2538_reg_t*)0x400890a8 ) 
#define AES_DMAC_CH0_CTRL           ( *(cc2538_reg_t*)0x4008b000 ) 
#define AES_DMAC_CH0_EXTADDR        ( *(cc2538_reg_t*)0x4008b004 ) 
#define AES_DMAC_CH0_DMALENGTH      ( *(cc2538_reg_t*)0x4008b00c ) 
#define AES_DMAC_STATUS             ( *(cc2538_reg_t*)0x4008b018 ) 
#define AES_DMAC_SWRES              ( *(cc2538_reg_t*)0x4008b01c ) 
#define AES_DMAC_CH1_CTRL           ( *(cc2538_reg_t*)0x4008b020 ) 
#define AES_DMAC_CH1_EXTADDR        ( *(cc2538_reg_t*)0x4008b024 ) 
#define AES_DMAC_CH1_DMALENGTH      ( *(cc2538_reg_t*)0x4008b02c ) 
#define AES_DMAC_MST_RUNPARAMS      ( *(cc2538_reg_t*)0x4008b078 ) 
#define AES_DMAC_PERSR              ( *(cc2538_reg_t*)0x4008b07c ) 
#define AES_DMAC_OPTIONS            ( *(cc2538_reg_t*)0x4008b0f8 ) 
#define AES_DMAC_VERSION            ( *(cc2538_reg_t*)0x4008b0fc ) 
#define AES_KEY_STORE_WRITE_AREA    ( *(cc2538_reg_t*)0x4008b400 ) 
#define AES_KEY_STORE_WRITTEN_AREA  ( *(cc2538_reg_t*)0x4008b404 ) 
#define AES_KEY_STORE_SIZE          ( *(cc2538_reg_t*)0x4008b408 ) 
#define AES_KEY_STORE_READ_AREA     ( *(cc2538_reg_t*)0x4008b40c ) 
#define AES_AES_KEY2_0              ( *(cc2538_reg_t*)0x4008b500 ) 
#define AES_AES_KEY2_1              ( *(cc2538_reg_t*)0x4008b504 ) 
#define AES_AES_KEY2_2              ( *(cc2538_reg_t*)0x4008b508 ) 
#define AES_AES_KEY2_3              ( *(cc2538_reg_t*)0x4008b50c ) 
#define AES_AES_KEY3_0              ( *(cc2538_reg_t*)0x4008b510 ) 
#define AES_AES_KEY3_1              ( *(cc2538_reg_t*)0x4008b514 ) 
#define AES_AES_KEY3_2              ( *(cc2538_reg_t*)0x4008b518 ) 
#define AES_AES_KEY3_3              ( *(cc2538_reg_t*)0x4008b51c ) 
#define AES_AES_IV_0                ( *(cc2538_reg_t*)0x4008b540 ) 
#define AES_AES_IV_1                ( *(cc2538_reg_t*)0x4008b544 ) 
#define AES_AES_IV_2                ( *(cc2538_reg_t*)0x4008b548 ) 
#define AES_AES_IV_3                ( *(cc2538_reg_t*)0x4008b54c ) 
#define AES_AES_CTRL                ( *(cc2538_reg_t*)0x4008b550 ) 
#define AES_AES_C_LENGTH_0          ( *(cc2538_reg_t*)0x4008b554 ) 
#define AES_AES_C_LENGTH_1          ( *(cc2538_reg_t*)0x4008b558 ) 
#define AES_AES_AUTH_LENGTH         ( *(cc2538_reg_t*)0x4008b55c ) 
#define AES_AES_DATA_IN_OUT_0       ( *(cc2538_reg_t*)0x4008b560 ) 
#define AES_AES_DATA_IN_OUT_1       ( *(cc2538_reg_t*)0x4008b564 ) 
#define AES_AES_DATA_IN_OUT_2       ( *(cc2538_reg_t*)0x4008b568 ) 
#define AES_AES_DATA_IN_OUT_3       ( *(cc2538_reg_t*)0x4008b56c ) 
#define AES_AES_TAG_OUT_0           ( *(cc2538_reg_t*)0x4008b570 ) 
#define AES_AES_TAG_OUT_1           ( *(cc2538_reg_t*)0x4008b574 ) 
#define AES_AES_TAG_OUT_2           ( *(cc2538_reg_t*)0x4008b578 ) 
#define AES_AES_TAG_OUT_3           ( *(cc2538_reg_t*)0x4008b57c ) 
#define AES_HASH_DATA_IN_0          ( *(cc2538_reg_t*)0x4008b600 ) 
#define AES_HASH_DATA_IN_1          ( *(cc2538_reg_t*)0x4008b604 ) 
#define AES_HASH_DATA_IN_2          ( *(cc2538_reg_t*)0x4008b608 ) 
#define AES_HASH_DATA_IN_3          ( *(cc2538_reg_t*)0x4008b60c ) 
#define AES_HASH_DATA_IN_4          ( *(cc2538_reg_t*)0x4008b610 ) 
#define AES_HASH_DATA_IN_5          ( *(cc2538_reg_t*)0x4008b614 ) 
#define AES_HASH_DATA_IN_6          ( *(cc2538_reg_t*)0x4008b618 ) 
#define AES_HASH_DATA_IN_7          ( *(cc2538_reg_t*)0x4008b61c ) 
#define AES_HASH_DATA_IN_8          ( *(cc2538_reg_t*)0x4008b620 ) 
#define AES_HASH_DATA_IN_9          ( *(cc2538_reg_t*)0x4008b624 ) 
#define AES_HASH_DATA_IN_10         ( *(cc2538_reg_t*)0x4008b628 ) 
#define AES_HASH_DATA_IN_11         ( *(cc2538_reg_t*)0x4008b62c ) 
#define AES_HASH_DATA_IN_12         ( *(cc2538_reg_t*)0x4008b630 ) 
#define AES_HASH_DATA_IN_13         ( *(cc2538_reg_t*)0x4008b634 ) 
#define AES_HASH_DATA_IN_14         ( *(cc2538_reg_t*)0x4008b638 ) 
#define AES_HASH_DATA_IN_15         ( *(cc2538_reg_t*)0x4008b63c ) 
#define AES_HASH_IO_BUF_CTRL        ( *(cc2538_reg_t*)0x4008b640 ) 
#define AES_HASH_MODE_IN            ( *(cc2538_reg_t*)0x4008b644 ) 
#define AES_HASH_LENGTH_IN_L        ( *(cc2538_reg_t*)0x4008b648 ) 
#define AES_HASH_LENGTH_IN_H        ( *(cc2538_reg_t*)0x4008b64c ) 
#define AES_HASH_DIGEST_A           ( *(cc2538_reg_t*)0x4008b650 ) 
#define AES_HASH_DIGEST_B           ( *(cc2538_reg_t*)0x4008b654 ) 
#define AES_HASH_DIGEST_C           ( *(cc2538_reg_t*)0x4008b658 ) 
#define AES_HASH_DIGEST_D           ( *(cc2538_reg_t*)0x4008b65c ) 
#define AES_HASH_DIGEST_E           ( *(cc2538_reg_t*)0x4008b660 ) 
#define AES_HASH_DIGEST_F           ( *(cc2538_reg_t*)0x4008b664 ) 
#define AES_HASH_DIGEST_G           ( *(cc2538_reg_t*)0x4008b668 ) 
#define AES_HASH_DIGEST_H           ( *(cc2538_reg_t*)0x4008b66c ) 
#define AES_CTRL_ALG_SEL            ( *(cc2538_reg_t*)0x4008b700 ) 
#define AES_CTRL_PROT_EN            ( *(cc2538_reg_t*)0x4008b704 ) 
#define AES_CTRL_SW_RESET           ( *(cc2538_reg_t*)0x4008b740 ) 
#define AES_CTRL_INT_CFG            ( *(cc2538_reg_t*)0x4008b780 ) 
#define AES_CTRL_INT_EN             ( *(cc2538_reg_t*)0x4008b784 ) 
#define AES_CTRL_INT_CLR            ( *(cc2538_reg_t*)0x4008b788 ) 
#define AES_CTRL_INT_SET            ( *(cc2538_reg_t*)0x4008b78c ) 
#define AES_CTRL_INT_STAT           ( *(cc2538_reg_t*)0x4008b790 ) 
#define AES_CTRL_OPTIONS            ( *(cc2538_reg_t*)0x4008b7f8 ) 
#define AES_CTRL_VERSION            ( *(cc2538_reg_t*)0x4008b7fc ) 
#define SYS_CTRL_CLOCK_CTRL         ( *(cc2538_reg_t*)0x400d2000 ) 
#define SYS_CTRL_CLOCK_STA          ( *(cc2538_reg_t*)0x400d2004 ) 
#define SYS_CTRL_RCGCGPT            ( *(cc2538_reg_t*)0x400d2008 ) 
#define SYS_CTRL_SCGCGPT            ( *(cc2538_reg_t*)0x400d200c ) 
#define SYS_CTRL_DCGCGPT            ( *(cc2538_reg_t*)0x400d2010 ) 
#define SYS_CTRL_SRGPT              ( *(cc2538_reg_t*)0x400d2014 ) 
#define SYS_CTRL_RCGCSSI            ( *(cc2538_reg_t*)0x400d2018 ) 
#define SYS_CTRL_SCGCSSI            ( *(cc2538_reg_t*)0x400d201c ) 
#define SYS_CTRL_DCGCSSI            ( *(cc2538_reg_t*)0x400d2020 ) 
#define SYS_CTRL_SRSSI              ( *(cc2538_reg_t*)0x400d2024 ) 
#define SYS_CTRL_RCGCUART           ( *(cc2538_reg_t*)0x400d2028 ) 
#define SYS_CTRL_SCGCUART           ( *(cc2538_reg_t*)0x400d202c ) 
#define SYS_CTRL_DCGCUART           ( *(cc2538_reg_t*)0x400d2030 ) 
#define SYS_CTRL_SRUART             ( *(cc2538_reg_t*)0x400d2034 ) 
#define SYS_CTRL_RCGCI2C            ( *(cc2538_reg_t*)0x400d2038 ) 
#define SYS_CTRL_SCGCI2C            ( *(cc2538_reg_t*)0x400d203c ) 
#define SYS_CTRL_DCGCI2C            ( *(cc2538_reg_t*)0x400d2040 ) 
#define SYS_CTRL_SRI2C              ( *(cc2538_reg_t*)0x400d2044 ) 
#define SYS_CTRL_RCGCSEC            ( *(cc2538_reg_t*)0x400d2048 ) 
#define SYS_CTRL_SCGCSEC            ( *(cc2538_reg_t*)0x400d204c ) 
#define SYS_CTRL_DCGCSEC            ( *(cc2538_reg_t*)0x400d2050 ) 
#define SYS_CTRL_SRSEC              ( *(cc2538_reg_t*)0x400d2054 ) 
#define SYS_CTRL_PMCTL              ( *(cc2538_reg_t*)0x400d2058 ) 
#define SYS_CTRL_SRCRC              ( *(cc2538_reg_t*)0x400d205c ) 
#define SYS_CTRL_PWRDBG             ( *(cc2538_reg_t*)0x400d2074 ) 
#define SYS_CTRL_CLD                ( *(cc2538_reg_t*)0x400d2080 ) 
#define SYS_CTRL_IWE                ( *(cc2538_reg_t*)0x400d2094 ) 
#define SYS_CTRL_I_MAP              ( *(cc2538_reg_t*)0x400d2098 ) 
#define SYS_CTRL_RCGCRFC            ( *(cc2538_reg_t*)0x400d20a8 ) 
#define SYS_CTRL_SCGCRFC            ( *(cc2538_reg_t*)0x400d20ac ) 
#define SYS_CTRL_DCGCRFC            ( *(cc2538_reg_t*)0x400d20b0 ) 
#define SYS_CTRL_EMUOVR             ( *(cc2538_reg_t*)0x400d20b4 ) 
#define FLASH_CTRL_FCTL             ( *(cc2538_reg_t*)0x400d3008 ) 
#define FLASH_CTRL_FADDR            ( *(cc2538_reg_t*)0x400d300c ) 
#define FLASH_CTRL_FWDATA           ( *(cc2538_reg_t*)0x400d3010 ) 
#define FLASH_CTRL_DIECFG0          ( *(cc2538_reg_t*)0x400d3014 ) 
#define FLASH_CTRL_DIECFG1          ( *(cc2538_reg_t*)0x400d3018 ) 
#define FLASH_CTRL_DIECFG2          ( *(cc2538_reg_t*)0x400d301c ) 
#define IOC_PA0_SEL                 ( *(cc2538_reg_t*)0x400d4000 ) 
#define IOC_PA1_SEL                 ( *(cc2538_reg_t*)0x400d4004 ) 
#define IOC_PA2_SEL                 ( *(cc2538_reg_t*)0x400d4008 ) 
#define IOC_PA3_SEL                 ( *(cc2538_reg_t*)0x400d400c ) 
#define IOC_PA4_SEL                 ( *(cc2538_reg_t*)0x400d4010 ) 
#define IOC_PA5_SEL                 ( *(cc2538_reg_t*)0x400d4014 ) 
#define IOC_PA6_SEL                 ( *(cc2538_reg_t*)0x400d4018 ) 
#define IOC_PA7_SEL                 ( *(cc2538_reg_t*)0x400d401c ) 
#define IOC_PB0_SEL                 ( *(cc2538_reg_t*)0x400d4020 ) 
#define IOC_PB1_SEL                 ( *(cc2538_reg_t*)0x400d4024 ) 
#define IOC_PB2_SEL                 ( *(cc2538_reg_t*)0x400d4028 ) 
#define IOC_PB3_SEL                 ( *(cc2538_reg_t*)0x400d402c ) 
#define IOC_PB4_SEL                 ( *(cc2538_reg_t*)0x400d4030 ) 
#define IOC_PB5_SEL                 ( *(cc2538_reg_t*)0x400d4034 ) 
#define IOC_PB6_SEL                 ( *(cc2538_reg_t*)0x400d4038 ) 
#define IOC_PB7_SEL                 ( *(cc2538_reg_t*)0x400d403c ) 
#define IOC_PC0_SEL                 ( *(cc2538_reg_t*)0x400d4040 ) 
#define IOC_PC1_SEL                 ( *(cc2538_reg_t*)0x400d4044 ) 
#define IOC_PC2_SEL                 ( *(cc2538_reg_t*)0x400d4048 ) 
#define IOC_PC3_SEL                 ( *(cc2538_reg_t*)0x400d404c ) 
#define IOC_PC4_SEL                 ( *(cc2538_reg_t*)0x400d4050 ) 
#define IOC_PC5_SEL                 ( *(cc2538_reg_t*)0x400d4054 ) 
#define IOC_PC6_SEL                 ( *(cc2538_reg_t*)0x400d4058 ) 
#define IOC_PC7_SEL                 ( *(cc2538_reg_t*)0x400d405c ) 
#define IOC_PD0_SEL                 ( *(cc2538_reg_t*)0x400d4060 ) 
#define IOC_PD1_SEL                 ( *(cc2538_reg_t*)0x400d4064 ) 
#define IOC_PD2_SEL                 ( *(cc2538_reg_t*)0x400d4068 ) 
#define IOC_PD3_SEL                 ( *(cc2538_reg_t*)0x400d406c ) 
#define IOC_PD4_SEL                 ( *(cc2538_reg_t*)0x400d4070 ) 
#define IOC_PD5_SEL                 ( *(cc2538_reg_t*)0x400d4074 ) 
#define IOC_PD6_SEL                 ( *(cc2538_reg_t*)0x400d4078 ) 
#define IOC_PD7_SEL                 ( *(cc2538_reg_t*)0x400d407c ) 
#define IOC_PA0_OVER                ( *(cc2538_reg_t*)0x400d4080 ) 
#define IOC_PA1_OVER                ( *(cc2538_reg_t*)0x400d4084 ) 
#define IOC_PA2_OVER                ( *(cc2538_reg_t*)0x400d4088 ) 
#define IOC_PA3_OVER                ( *(cc2538_reg_t*)0x400d408c ) 
#define IOC_PA4_OVER                ( *(cc2538_reg_t*)0x400d4090 ) 
#define IOC_PA5_OVER                ( *(cc2538_reg_t*)0x400d4094 ) 
#define IOC_PA6_OVER                ( *(cc2538_reg_t*)0x400d4098 ) 
#define IOC_PA7_OVER                ( *(cc2538_reg_t*)0x400d409c ) 
#define IOC_PB0_OVER                ( *(cc2538_reg_t*)0x400d40a0 ) 
#define IOC_PB1_OVER                ( *(cc2538_reg_t*)0x400d40a4 ) 
#define IOC_PB2_OVER                ( *(cc2538_reg_t*)0x400d40a8 ) 
#define IOC_PB3_OVER                ( *(cc2538_reg_t*)0x400d40ac ) 
#define IOC_PB4_OVER                ( *(cc2538_reg_t*)0x400d40b0 ) 
#define IOC_PB5_OVER                ( *(cc2538_reg_t*)0x400d40b4 ) 
#define IOC_PB6_OVER                ( *(cc2538_reg_t*)0x400d40b8 ) 
#define IOC_PB7_OVER                ( *(cc2538_reg_t*)0x400d40bc ) 
#define IOC_PC0_OVER                ( *(cc2538_reg_t*)0x400d40c0 ) 
#define IOC_PC1_OVER                ( *(cc2538_reg_t*)0x400d40c4 ) 
#define IOC_PC2_OVER                ( *(cc2538_reg_t*)0x400d40c8 ) 
#define IOC_PC3_OVER                ( *(cc2538_reg_t*)0x400d40cc ) 
#define IOC_PC4_OVER                ( *(cc2538_reg_t*)0x400d40d0 ) 
#define IOC_PC5_OVER                ( *(cc2538_reg_t*)0x400d40d4 ) 
#define IOC_PC6_OVER                ( *(cc2538_reg_t*)0x400d40d8 ) 
#define IOC_PC7_OVER                ( *(cc2538_reg_t*)0x400d40dc ) 
#define IOC_PD0_OVER                ( *(cc2538_reg_t*)0x400d40e0 ) 
#define IOC_PD1_OVER                ( *(cc2538_reg_t*)0x400d40e4 ) 
#define IOC_PD2_OVER                ( *(cc2538_reg_t*)0x400d40e8 ) 
#define IOC_PD3_OVER                ( *(cc2538_reg_t*)0x400d40ec ) 
#define IOC_PD4_OVER                ( *(cc2538_reg_t*)0x400d40f0 ) 
#define IOC_PD5_OVER                ( *(cc2538_reg_t*)0x400d40f4 ) 
#define IOC_PD6_OVER                ( *(cc2538_reg_t*)0x400d40f8 ) 
#define IOC_PD7_OVER                ( *(cc2538_reg_t*)0x400d40fc ) 
#define IOC_UARTRXD_UART0           ( *(cc2538_reg_t*)0x400d4100 ) 
#define IOC_UARTCTS_UART1           ( *(cc2538_reg_t*)0x400d4104 ) 
#define IOC_UARTRXD_UART1           ( *(cc2538_reg_t*)0x400d4108 ) 
#define IOC_CLK_SSI_SSI0            ( *(cc2538_reg_t*)0x400d410c ) 
#define IOC_SSIRXD_SSI0             ( *(cc2538_reg_t*)0x400d4110 ) 
#define IOC_SSIFSSIN_SSI0           ( *(cc2538_reg_t*)0x400d4114 ) 
#define IOC_CLK_SSIIN_SSI0          ( *(cc2538_reg_t*)0x400d4118 ) 
#define IOC_CLK_SSI_SSI1            ( *(cc2538_reg_t*)0x400d411c ) 
#define IOC_SSIRXD_SSI1             ( *(cc2538_reg_t*)0x400d4120 ) 
#define IOC_SSIFSSIN_SSI1           ( *(cc2538_reg_t*)0x400d4124 ) 
#define IOC_CLK_SSIIN_SSI1          ( *(cc2538_reg_t*)0x400d4128 ) 
#define IOC_I2CMSSDA                ( *(cc2538_reg_t*)0x400d412c ) 
#define IOC_I2CMSSCL                ( *(cc2538_reg_t*)0x400d4130 ) 
#define IOC_GPT0OCP1                ( *(cc2538_reg_t*)0x400d4134 ) 
#define IOC_GPT0OCP2                ( *(cc2538_reg_t*)0x400d4138 ) 
#define IOC_GPT1OCP1                ( *(cc2538_reg_t*)0x400d413c ) 
#define IOC_GPT1OCP2                ( *(cc2538_reg_t*)0x400d4140 ) 
#define IOC_GPT2OCP1                ( *(cc2538_reg_t*)0x400d4144 ) 
#define IOC_GPT2OCP2                ( *(cc2538_reg_t*)0x400d4148 ) 
#define IOC_GPT3OCP1                ( *(cc2538_reg_t*)0x400d414c ) 
#define IOC_GPT3OCP2                ( *(cc2538_reg_t*)0x400d4150 ) 
#define SMWDTHROSC_WDCTL            ( *(cc2538_reg_t*)0x400d5000 ) 
#define SMWDTHROSC_ST0              ( *(cc2538_reg_t*)0x400d5040 ) 
#define SMWDTHROSC_ST1              ( *(cc2538_reg_t*)0x400d5044 ) 
#define SMWDTHROSC_ST2              ( *(cc2538_reg_t*)0x400d5048 ) 
#define SMWDTHROSC_ST3              ( *(cc2538_reg_t*)0x400d504c ) 
#define SMWDTHROSC_STLOAD           ( *(cc2538_reg_t*)0x400d5050 ) 
#define SMWDTHROSC_STCC             ( *(cc2538_reg_t*)0x400d5054 ) 
#define SMWDTHROSC_STCS             ( *(cc2538_reg_t*)0x400d5058 ) 
#define SMWDTHROSC_STCV0            ( *(cc2538_reg_t*)0x400d505c ) 
#define SMWDTHROSC_STCV1            ( *(cc2538_reg_t*)0x400d5060 ) 
#define SMWDTHROSC_STCV2            ( *(cc2538_reg_t*)0x400d5064 ) 
#define SMWDTHROSC_STCV3            ( *(cc2538_reg_t*)0x400d5068 ) 
#define ANA_REGS_IVCTRL             ( *(cc2538_reg_t*)0x400d6004 ) 
#define GPIO_A_DATA                 ( *(cc2538_reg_t*)0x400d9000 ) 
#define GPIO_A_DIR                  ( *(cc2538_reg_t*)0x400d9400 ) 
#define GPIO_A_IS                   ( *(cc2538_reg_t*)0x400d9404 ) 
#define GPIO_A_IBE                  ( *(cc2538_reg_t*)0x400d9408 ) 
#define GPIO_A_IEV                  ( *(cc2538_reg_t*)0x400d940c ) 
#define GPIO_A_IE                   ( *(cc2538_reg_t*)0x400d9410 ) 
#define GPIO_A_RIS                  ( *(cc2538_reg_t*)0x400d9414 ) 
#define GPIO_A_MIS                  ( *(cc2538_reg_t*)0x400d9418 ) 
#define GPIO_A_IC                   ( *(cc2538_reg_t*)0x400d941c ) 
#define GPIO_A_AFSEL                ( *(cc2538_reg_t*)0x400d9420 ) 
#define GPIO_A_GPIOLOCK             ( *(cc2538_reg_t*)0x400d9520 ) 
#define GPIO_A_GPIOCR               ( *(cc2538_reg_t*)0x400d9524 ) 
#define GPIO_A_PMUX                 ( *(cc2538_reg_t*)0x400d9700 ) 
#define GPIO_A_P_EDGE_CTRL          ( *(cc2538_reg_t*)0x400d9704 ) 
#define GPIO_A_PI_IEN               ( *(cc2538_reg_t*)0x400d9710 ) 
#define GPIO_A_IRQ_DETECT_ACK       ( *(cc2538_reg_t*)0x400d9718 ) 
#define GPIO_A_USB_IRQ_ACK          ( *(cc2538_reg_t*)0x400d971c ) 
#define GPIO_A_IRQ_DETECT_UNMASK    ( *(cc2538_reg_t*)0x400d9720 ) 
#define GPIO_B_DATA                 ( *(cc2538_reg_t*)0x400da000 ) 
#define GPIO_B_DIR                  ( *(cc2538_reg_t*)0x400da400 ) 
#define GPIO_B_IS                   ( *(cc2538_reg_t*)0x400da404 ) 
#define GPIO_B_IBE                  ( *(cc2538_reg_t*)0x400da408 ) 
#define GPIO_B_IEV                  ( *(cc2538_reg_t*)0x400da40c ) 
#define GPIO_B_IE                   ( *(cc2538_reg_t*)0x400da410 ) 
#define GPIO_B_RIS                  ( *(cc2538_reg_t*)0x400da414 ) 
#define GPIO_B_MIS                  ( *(cc2538_reg_t*)0x400da418 ) 
#define GPIO_B_IC                   ( *(cc2538_reg_t*)0x400da41c ) 
#define GPIO_B_AFSEL                ( *(cc2538_reg_t*)0x400da420 ) 
#define GPIO_B_GPIOLOCK             ( *(cc2538_reg_t*)0x400da520 ) 
#define GPIO_B_GPIOCR               ( *(cc2538_reg_t*)0x400da524 ) 
#define GPIO_B_PMUX                 ( *(cc2538_reg_t*)0x400da700 ) 
#define GPIO_B_P_EDGE_CTRL          ( *(cc2538_reg_t*)0x400da704 ) 
#define GPIO_B_PI_IEN               ( *(cc2538_reg_t*)0x400da710 ) 
#define GPIO_B_IRQ_DETECT_ACK       ( *(cc2538_reg_t*)0x400da718 ) 
#define GPIO_B_USB_IRQ_ACK          ( *(cc2538_reg_t*)0x400da71c ) 
#define GPIO_B_IRQ_DETECT_UNMASK    ( *(cc2538_reg_t*)0x400da720 ) 
#define GPIO_C_DATA                 ( *(cc2538_reg_t*)0x400db000 ) 
#define GPIO_C_DIR                  ( *(cc2538_reg_t*)0x400db400 ) 
#define GPIO_C_IS                   ( *(cc2538_reg_t*)0x400db404 ) 
#define GPIO_C_IBE                  ( *(cc2538_reg_t*)0x400db408 ) 
#define GPIO_C_IEV                  ( *(cc2538_reg_t*)0x400db40c ) 
#define GPIO_C_IE                   ( *(cc2538_reg_t*)0x400db410 ) 
#define GPIO_C_RIS                  ( *(cc2538_reg_t*)0x400db414 ) 
#define GPIO_C_MIS                  ( *(cc2538_reg_t*)0x400db418 ) 
#define GPIO_C_IC                   ( *(cc2538_reg_t*)0x400db41c ) 
#define GPIO_C_AFSEL                ( *(cc2538_reg_t*)0x400db420 ) 
#define GPIO_C_GPIOLOCK             ( *(cc2538_reg_t*)0x400db520 ) 
#define GPIO_C_GPIOCR               ( *(cc2538_reg_t*)0x400db524 ) 
#define GPIO_C_PMUX                 ( *(cc2538_reg_t*)0x400db700 ) 
#define GPIO_C_P_EDGE_CTRL          ( *(cc2538_reg_t*)0x400db704 ) 
#define GPIO_C_PI_IEN               ( *(cc2538_reg_t*)0x400db710 ) 
#define GPIO_C_IRQ_DETECT_ACK       ( *(cc2538_reg_t*)0x400db718 ) 
#define GPIO_C_USB_IRQ_ACK          ( *(cc2538_reg_t*)0x400db71c ) 
#define GPIO_C_IRQ_DETECT_UNMASK    ( *(cc2538_reg_t*)0x400db720 ) 
#define GPIO_D_DATA                 ( *(cc2538_reg_t*)0x400dc000 ) 
#define GPIO_D_DIR                  ( *(cc2538_reg_t*)0x400dc400 ) 
#define GPIO_D_IS                   ( *(cc2538_reg_t*)0x400dc404 ) 
#define GPIO_D_IBE                  ( *(cc2538_reg_t*)0x400dc408 ) 
#define GPIO_D_IEV                  ( *(cc2538_reg_t*)0x400dc40c ) 
#define GPIO_D_IE                   ( *(cc2538_reg_t*)0x400dc410 ) 
#define GPIO_D_RIS                  ( *(cc2538_reg_t*)0x400dc414 ) 
#define GPIO_D_MIS                  ( *(cc2538_reg_t*)0x400dc418 ) 
#define GPIO_D_IC                   ( *(cc2538_reg_t*)0x400dc41c ) 
#define GPIO_D_AFSEL                ( *(cc2538_reg_t*)0x400dc420 ) 
#define GPIO_D_GPIOLOCK             ( *(cc2538_reg_t*)0x400dc520 ) 
#define GPIO_D_GPIOCR               ( *(cc2538_reg_t*)0x400dc524 ) 
#define GPIO_D_PMUX                 ( *(cc2538_reg_t*)0x400dc700 ) 
#define GPIO_D_P_EDGE_CTRL          ( *(cc2538_reg_t*)0x400dc704 ) 
#define GPIO_D_PI_IEN               ( *(cc2538_reg_t*)0x400dc710 ) 
#define GPIO_D_IRQ_DETECT_ACK       ( *(cc2538_reg_t*)0x400dc718 ) 
#define GPIO_D_USB_IRQ_ACK          ( *(cc2538_reg_t*)0x400dc71c ) 
#define GPIO_D_IRQ_DETECT_UNMASK    ( *(cc2538_reg_t*)0x400dc720 ) 
#define UDMA_STAT                   ( *(cc2538_reg_t*)0x400ff000 ) 
#define UDMA_CFG                    ( *(cc2538_reg_t*)0x400ff004 ) 
#define UDMA_CTLBASE                ( *(cc2538_reg_t*)0x400ff008 ) 
#define UDMA_ALTBASE                ( *(cc2538_reg_t*)0x400ff00c ) 
#define UDMA_WAITSTAT               ( *(cc2538_reg_t*)0x400ff010 ) 
#define UDMA_SWREQ                  ( *(cc2538_reg_t*)0x400ff014 ) 
#define UDMA_USEBURSTSET            ( *(cc2538_reg_t*)0x400ff018 ) 
#define UDMA_USEBURSTCLR            ( *(cc2538_reg_t*)0x400ff01c ) 
#define UDMA_REQMASKSET             ( *(cc2538_reg_t*)0x400ff020 ) 
#define UDMA_REQMASKCLR             ( *(cc2538_reg_t*)0x400ff024 ) 
#define UDMA_ENASET                 ( *(cc2538_reg_t*)0x400ff028 ) 
#define UDMA_ENACLR                 ( *(cc2538_reg_t*)0x400ff02c ) 
#define UDMA_ALTSET                 ( *(cc2538_reg_t*)0x400ff030 ) 
#define UDMA_ALTCLR                 ( *(cc2538_reg_t*)0x400ff034 ) 
#define UDMA_PRIOSET                ( *(cc2538_reg_t*)0x400ff038 ) 
#define UDMA_PRIOCLR                ( *(cc2538_reg_t*)0x400ff03c ) 
#define UDMA_ERRCLR                 ( *(cc2538_reg_t*)0x400ff04c ) 
#define UDMA_CHASGN                 ( *(cc2538_reg_t*)0x400ff500 ) 
#define UDMA_CHIS                   ( *(cc2538_reg_t*)0x400ff504 ) 
#define UDMA_CHMAP0                 ( *(cc2538_reg_t*)0x400ff510 ) 
#define UDMA_CHMAP1                 ( *(cc2538_reg_t*)0x400ff514 ) 
#define UDMA_CHMAP2                 ( *(cc2538_reg_t*)0x400ff518 ) 
#define UDMA_CHMAP3                 ( *(cc2538_reg_t*)0x400ff51c ) 
#define PKA_APTR                    ( *(cc2538_reg_t*)0x44004000 ) 
#define PKA_BPTR                    ( *(cc2538_reg_t*)0x44004004 ) 
#define PKA_CPTR                    ( *(cc2538_reg_t*)0x44004008 ) 
#define PKA_DPTR                    ( *(cc2538_reg_t*)0x4400400c ) 
#define PKA_ALENGTH                 ( *(cc2538_reg_t*)0x44004010 ) 
#define PKA_BLENGTH                 ( *(cc2538_reg_t*)0x44004014 ) 
#define PKA_SHIFT                   ( *(cc2538_reg_t*)0x44004018 ) 
#define PKA_FUNCTION                ( *(cc2538_reg_t*)0x4400401c ) 
#define PKA_COMPARE                 ( *(cc2538_reg_t*)0x44004020 ) 
#define PKA_MSW                     ( *(cc2538_reg_t*)0x44004024 ) 
#define PKA_DIVMSW                  ( *(cc2538_reg_t*)0x44004028 ) 
#define PKA_SEQ_CTRL                ( *(cc2538_reg_t*)0x440040c8 ) 
#define PKA_OPTIONS                 ( *(cc2538_reg_t*)0x440040f4 ) 
#define PKA_SW_REV                  ( *(cc2538_reg_t*)0x440040f8 ) 
#define PKA_REVISION                ( *(cc2538_reg_t*)0x440040fc ) 
#define CCTEST_IO                   ( *(cc2538_reg_t*)0x44010000 ) 
#define CCTEST_OBSSEL0              ( *(cc2538_reg_t*)0x44010014 ) 
#define CCTEST_OBSSEL1              ( *(cc2538_reg_t*)0x44010018 ) 
#define CCTEST_OBSSEL2              ( *(cc2538_reg_t*)0x4401001c ) 
#define CCTEST_OBSSEL3              ( *(cc2538_reg_t*)0x44010020 ) 
#define CCTEST_OBSSEL4              ( *(cc2538_reg_t*)0x44010024 ) 
#define CCTEST_OBSSEL5              ( *(cc2538_reg_t*)0x44010028 ) 
#define CCTEST_OBSSEL6              ( *(cc2538_reg_t*)0x4401002c ) 
#define CCTEST_OBSSEL7              ( *(cc2538_reg_t*)0x44010030 ) 
#define CCTEST_TR0                  ( *(cc2538_reg_t*)0x44010034 ) 
#define CCTEST_USBCTRL              ( *(cc2538_reg_t*)0x44010050 ) 
#define XOSC32M_FREQ                32000000U 
#define RCOSC16M_FREQ               16000000U 
#define XOSC32K_FREQ                   32768U 
#define RCOSC32K_FREQ                  32753U 
#define CC2538_VTOR_ALIGN                 512 
#ifdef __cplusplus
}
#endif
 
#endif /* CC2538_H */