cc2538_rf.h

Go to the documentation of this file.

/*
 * Copyright (C) 2016 MUTEX NZ Ltd.
 * Copyright (C) 2015 Loci Controls Inc.
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 *
 */
 
#ifndef CC2538_RF_H
#define CC2538_RF_H
 
#include <stdbool.h>
 
#include "board.h"
 
#include "net/ieee802154.h"
#include "kernel_defines.h"
 
#if IS_USED(MODULE_IEEE802154_RADIO_HAL)
#include "net/ieee802154/radio.h"
#if IS_USED(MODULE_NETDEV_IEEE802154_SUBMAC)
#include "net/netdev/ieee802154_submac.h"
#endif
#else
#include "net/netdev.h"
#include "net/netdev/ieee802154.h"
#endif
 
#include "net/netopt.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CC2538_AUTOCRC_LEN          (2)
#define CC2538_RF_FIFO_SIZE         (128)
#define CC2538_PACKET_LENGTH_SIZE   (1)
 
#define CC2538_RF_MAX_DATA_LEN (CC2538_RF_FIFO_SIZE - CC2538_PACKET_LENGTH_SIZE)
 
/* TODO: Move these to sys/include/net/ieee802154.h somehow */
/* IEEE 802.15.4 defined constants (2.4 GHz logical channels) */
#define IEEE802154_MIN_FREQ         (2405) 
#define IEEE802154_MAX_FREQ         (2480) 
#define IEEE802154_CHANNEL_SPACING  (5)    
#define IEEE802154_CHAN2FREQ(chan)  ( IEEE802154_MIN_FREQ + ((chan) - IEEE802154_CHANNEL_MIN) * IEEE802154_CHANNEL_SPACING )
#define IEEE802154_FREQ2CHAN(freq)  ( IEEE802154_CHANNEL_MIN + ((freq) - IEEE802154_MIN_FREQ) / IEEE802154_CHANNEL_SPACING )
/* /TODO */
 
#define CC2538_MIN_FREQ             (2394)
#define CC2538_MAX_FREQ             (2507)
 
#define CC2538_RF_POWER_DEFAULT     (CONFIG_IEEE802154_DEFAULT_TXPOWER)    
#define CC2538_RF_CHANNEL_DEFAULT   (CONFIG_IEEE802154_DEFAULT_CHANNEL)
 
#define OUTPUT_POWER_MIN            (-24)  
#define OUTPUT_POWER_MAX            (7)    
#define NUM_POWER_LEVELS            ( OUTPUT_POWER_MAX - OUTPUT_POWER_MIN + 1 )
 
#define CC2538_CORR_VAL_MIN         (50U)
#define CC2538_CORR_VAL_MAX         (110U)
#define CC2538_CORR_VAL_MASK        (0x7F)
 
#define CC2538_CRC_BIT_MASK         (0x80)
 
#define CC2538_CCA_THR_MASK         (0x000000FF)    
#define CC2538_CCA_MODE_MASK        (0x18)          
#define CC2538_CCA_MODE_POS         (3U)            
#define CC2538_CSP_SKIP_INST_MASK   (0x70)          
#define CC2538_CSP_SKIP_INST_POS    (4U)            
#define CC2538_CSP_SKIP_N_MASK      (0x08)          
#define CC2538_CSP_SKIP_COND_CCA    (0x00)          
#define CC2538_CSP_SKIP_COND_CSPZ   (0x06)          
#define CC2538_CSP_SKIP_COND_RSSI   (0x07)          
#define CC2538_SFR_MTMSEL_MASK      (0x7)           
#define CC2538_SFR_MTMSEL_TIMER_P   (0x2)           
#define CC2538_MCTRL_SYNC_MASK      (0x2)           
#define CC2538_MCTRL_RUN_MASK       (0x1)           
#define CC2538_CSP_MCU_CTRL_MASK    (0x1)           
#define CC2538_CSP_INCMAXY_MAX_MASK (0x7)           
#define CC2538_RXENABLE_RXON_MASK   (0x80)          
#define CC2538_RSSI_OFFSET          (-73)  
#define CC2538_RF_SENSITIVITY       (-97)  
#define CC2538_ACCEPT_FT_2_ACK           (1 << 5) 
#define CC2538_STATE_SFD_WAIT_RANGE_MIN  (0x03U)  
#define CC2538_STATE_SFD_WAIT_RANGE_MAX  (0x06U)  
#define CC2538_FRMCTRL1_PENDING_OR_MASK  (0x04)   
#define RFCORE_ASSERT(expr) (void)( (expr) || RFCORE_ASSERT_failure(#expr, __FUNCTION__, __LINE__) )
 
#if DEVELHELP
#define RFCORE_WAIT_UNTIL(expr) while (!(expr)) {                                        \
    DEBUG("RFCORE_WAIT_UNTIL(%s) at line %u in %s()\n", #expr, __LINE__, __FUNCTION__);  \
    thread_yield();                                                                      \
}
#else
#define RFCORE_WAIT_UNTIL(expr) while (!(expr)) thread_yield()
#endif
 
#define RFCORE_FLUSH_RECEIVE_FIFO() rfcore_strobe(ISFLUSHRX)
 
#define ABS_DIFF(x, y)          ( ((x) < (y))? ((y) - (x)) : ((x) - (y)) )
#define BOOLEAN(x)              ( (x) != 0 )
#define NOT(x)                  ( (x) == 0 )
#define GET_BYTE(buffer, index) ( (unsigned char*)(buffer) )[index]
 
#define BIT(n) ( 1 << (n) )
 
enum {
    FSM_STATE_IDLE           =  0,
    FSM_STATE_RX_CALIBRATION =  2,
    FSM_STATE_TX_CALIBRATION = 32,
};
 
/*
 * @brief RFCORE_XREG_RFERRM bits
 */
enum {
    STROBE_ERR = BIT(6),
    TXUNDERF   = BIT(5),
    TXOVERF    = BIT(4),
    RXUNDERF   = BIT(3),
    RXOVERF    = BIT(2),
    RXABO      = BIT(1),
    NLOCK      = BIT(0),
};
 
 /*
  * @brief RFCORE_XREG_FRMCTRL0 bits
  */
enum {
    SET_RXENMASK_ON_TX  = BIT(0),
    IGNORE_TX_UNDERF    = BIT(1),
    PENDING_OR          = BIT(2),
};
 
 /*
  * @brief RFCORE_XREG_FRMCTRL1 bits
  */
enum {
    ENERGY_SCAN      = BIT(4),
    AUTOACK          = BIT(5),
    AUTOCRC          = BIT(6),
    APPEND_DATA_MODE = BIT(7),
};
 
/*
 * @brief RFCORE_XREG_RFIRQM0 / RFCORE_XREG_RFIRQF0 bits
 */
enum {
    ACT_UNUSED       = BIT(0),
    SFD              = BIT(1), 
    FIFOP            = BIT(2),
    SRC_MATCH_DONE   = BIT(3),
    SRC_MATCH_FOUND  = BIT(4),
    FRAME_ACCEPTED   = BIT(5),
    RXPKTDONE        = BIT(6), 
    RXMASKZERO       = BIT(7),
};
 
/*
 * @brief RFCORE_XREG_RFIRQM1 / RFCORE_XREG_RFIRQF1 bits
 */
enum {
    TXACKDONE        = BIT(0),
    TXDONE           = BIT(1),
    RF_IDLE          = BIT(2),
    CSP_MANINT       = BIT(3),
    CSP_STOP         = BIT(4),
    CSP_WAIT         = BIT(5),
};
 
/* Values for use with CCTEST_OBSSELx registers: */
enum {
    rfc_obs_sig0 = 0,
    rfc_obs_sig1 = 1,
    rfc_obs_sig2 = 2,
};
 
/* Values for RFCORE_XREG_RFC_OBS_CTRLx registers: */
enum {
    constant_value_0 = 0x00, 
    constant_value_1 = 0x01, 
    rfc_sniff_data   = 0x08, 
    rfc_sniff_clk    = 0x09, 
    rssi_valid       = 0x0c, 
    demod_cca        = 0x0d, 
    sampled_cca      = 0x0e, 
    sfd_sync         = 0x0f, 
    tx_active        = 0x10, 
    rx_active        = 0x11, 
    ffctrl_fifo      = 0x12, 
    ffctrl_fifop     = 0x13, 
    packet_done      = 0x14, 
    rfc_xor_rand_i_q = 0x16, 
    rfc_rand_q       = 0x17, 
    rfc_rand_i       = 0x18, 
    lock_status      = 0x19, 
    pa_pd            = 0x20, 
    lna_pd           = 0x2a, 
    disabled         = 0xff, 
};
 
#ifndef CONFIG_CC2538_RF_OBS_0
#define CONFIG_CC2538_RF_OBS_0      tx_active
#endif
#ifndef CONFIG_CC2538_RF_OBS_1
#define CONFIG_CC2538_RF_OBS_1      rx_active
#endif
#ifndef CONFIG_CC2538_RF_OBS_2
#define CONFIG_CC2538_RF_OBS_2      rssi_valid
#endif
 
/* Default configuration for cc2538dk or similar */
#ifndef CONFIG_CC2538_RF_OBS_SIG_0_PCX
#define CONFIG_CC2538_RF_OBS_SIG_0_PCX  0   /* PC0 = LED_1 (red) */
#endif
#ifndef CONFIG_CC2538_RF_OBS_SIG_1_PCX
#define CONFIG_CC2538_RF_OBS_SIG_1_PCX  1   /* PC0 = LED_2 (red) */
#endif
#ifndef CONFIG_CC2538_RF_OBS_SIG_2_PCX
#define CONFIG_CC2538_RF_OBS_SIG_2_PCX  2   /* PC0 = LED_3 (red) */
#endif
#if ((CONFIG_CC2538_RF_OBS_SIG_2_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_1_PCX > 7) || \
     (CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
#error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"
#endif
 
typedef struct {
#if IS_USED(MODULE_NETDEV_IEEE802154_SUBMAC)
    netdev_ieee802154_submac_t netdev;   
#elif !IS_USED(MODULE_IEEE802154_RADIO_HAL)
    netdev_ieee802154_t netdev;   
#endif
    uint8_t state;                
} cc2538_rf_t;
 
void cc2538_irq_handler(void);
 
bool cc2538_channel_clear(void);
 
void cc2538_get_addr_long(uint8_t *addr);
 
void cc2538_get_addr_short(uint8_t *addr);
 
unsigned int cc2538_get_chan(void);
 
bool cc2538_get_monitor(void);
 
uint16_t cc2538_get_pan(void);
 
int cc2538_get_tx_power(void);
 
void cc2538_init(void);
 
bool cc2538_is_on(void);
 
void cc2538_off(void);
 
bool cc2538_on(void);
 
void cc2538_setup(cc2538_rf_t *dev);
 
void cc2538_set_addr_short(const uint8_t *addr);
 
void cc2538_set_addr_long(const uint8_t *addr);
 
void cc2538_set_chan(unsigned int chan);
 
void cc2538_set_freq(unsigned int MHz);
 
void cc2538_set_monitor(bool mode);
 
void cc2538_set_pan(uint16_t pan);
 
void cc2538_set_state(cc2538_rf_t *dev, netopt_state_t state);
 
void cc2538_set_tx_power(int dBm);
 
#ifdef __cplusplus
}
#endif
 
#endif /* CC2538_RF_H */