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19 #ifndef PERIPH_CPU_COMMON_H
20 #define PERIPH_CPU_COMMON_H
31 #define CPUID_ADDR (&FCFG->MAC_BLE_0)
35 #define CPUID_LEN (16U)
41 #define PROVIDES_PM_SET_LOWEST_CORTEXM
48 #define HAVE_GPIO_MODE_T
61 #define HAVE_GPIO_FLANK_T
74 #define UART_INVALID_MODE (0x8000000)
80 #define HAVE_UART_PARITY_T
94 #define HAVE_UART_DATA_BITS_T
107 #define HAVE_UART_STOP_BITS_T
122 #ifdef MODULE_PERIPH_UART_HW_FC
141 #define PERIPH_I2C_NEED_READ_REG
142 #define PERIPH_I2C_NEED_READ_REGS
143 #define PERIPH_I2C_NEED_WRITE_REG
144 #define PERIPH_I2C_NEED_WRITE_REGS
@ UART_PARITY_NONE
no parity
@ UART_DATA_BITS_5
5 data bits
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
@ GPIO_IN_PD
configure as input with pull-down resistor
@ UART_STOP_BITS_2
2 stop bits
@ GPIO_OD
configure as output in open-drain mode without pull resistor
UART component registers.
@ UART_DATA_BITS_8
8 data bits
#define IOCFG_EDGEDET_FALLING
edge detection on falling edge
@ GPIO_OUT
configure as output in push-pull mode
@ UART_DATA_BITS_6
6 data bits
uart_parity_t
Definition of possible parity modes.
@ GPIO_FALLING
emit interrupt on falling flank
#define IOCFG_PULLCTL_UP
pull up
@ GPIO_IN_PU
configure as input with pull-up resistor
@ GPIO_RISING
emit interrupt on rising flank
@ GPIO_IN
configure as input without pull resistor
UART device configuration.
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
@ UART_PARITY_SPACE
space parity
#define IOCFG_EDGEDET_RISING
edge detection on rising edge
#define IOCFG_PULLCTL_DOWN
pull down
#define IOCFG_IOMODE_OPEN_DRAIN
open drain
@ GPIO_BOTH
emit interrupt on both flanks
@ UART_PARITY_EVEN
even parity
gpio_mode_t
Available pin modes.
@ UART_DATA_BITS_7
7 data bits
@ UART_PARITY_MARK
mark parity
@ UART_STOP_BITS_1
1 stop bit
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
@ UART_PARITY_ODD
odd parity
#define IOCFG_EDGEDET_BOTH
edge detection on both edges
#define IOCFG_PULLCTL_OFF
no IO pull