periph_cpu.h

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/*
 * Copyright (C) 2015-2016 Freie Universität Berlin
 *               2017 HAW Hamburg
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <stdint.h>
#include <stdio.h>
 
#include "vendor/hw_soc_adc.h"
 
#include "cpu.h"
#include "vendor/hw_ssi.h"
#include "vendor/hw_uart.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CPUID_ADDR          (&IEEE_ADDR_MSWORD)
 
#define CPUID_LEN           (8U)
 
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
#define PM_NUM_MODES        (4)
 
#define GPIO_UNDEF          (0xffffffff)
 
#define GPIO_MUX_NONE       (0xff)
 
#define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
                                      (port << GPIO_PORTNUM_SHIFT)) | pin)
 
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
 
void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func);
 
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
 
#ifndef DOXYGEN
 
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       = 0x01,     
    I2C_SPEED_NORMAL    = 100000U,  
    I2C_SPEED_FAST      = 400000U,  
    I2C_SPEED_FAST_PLUS = 0x02,     
    I2C_SPEED_HIGH      = 0x03,     
} i2c_speed_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    i2c_speed_t speed;      
    gpio_t scl_pin;         
    gpio_t sda_pin;         
} i2c_conf_t;
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 
#ifndef DOXYGEN
 
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN         = ((uint8_t)OVERRIDE_DISABLE),      
    GPIO_IN_ANALOG  = ((uint8_t)OVERRIDE_ANALOG),       
    GPIO_IN_PD      = ((uint8_t)OVERRIDE_PULLDOWN),     
    GPIO_IN_PU      = ((uint8_t)OVERRIDE_PULLUP),       
    GPIO_OUT        = ((uint8_t)OVERRIDE_ENABLE),       
    GPIO_OD         = (0xff),                           
    GPIO_OD_PU      = (0xff)                            
} gpio_mode_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    cc2538_uart_t *dev;       
    gpio_t rx_pin;            
    gpio_t tx_pin;            
#ifdef MODULE_PERIPH_UART_HW_FC
    gpio_t cts_pin;           
    gpio_t rts_pin;           
#endif
} uart_conf_t;
#ifndef DOXYGEN
 
#define HAVE_UART_PARITY_T
typedef enum {
   UART_PARITY_NONE = 0,                                                
   UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS),                  
   UART_PARITY_ODD = UART_LCRH_PEN,                                     
   UART_PARITY_MARK = (UART_LCRH_PEN | UART_LCRH_SPS),                  
   UART_PARITY_SPACE = (UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_SPS)  
} uart_parity_t;
#define HAVE_UART_DATA_BITS_T
typedef enum {
    UART_DATA_BITS_5 = (0 << UART_LCRH_WLEN_S),     
    UART_DATA_BITS_6 = (1 << UART_LCRH_WLEN_S),     
    UART_DATA_BITS_7 = (2 << UART_LCRH_WLEN_S),     
    UART_DATA_BITS_8 = (3 << UART_LCRH_WLEN_S),     
} uart_data_bits_t;
#define HAVE_UART_STOP_BITS_T
typedef enum {
   UART_STOP_BITS_1 = 0,                  
   UART_STOP_BITS_2 = UART_LCRH_STP2,     
} uart_stop_bits_t;
#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = 0,                             
    SPI_MODE_1 = (SSI_CR0_SPH),                 
    SPI_MODE_2 = (SSI_CR0_SPO),                 
    SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)    
} spi_mode_t;
#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ = 0,     
    SPI_CLK_400KHZ = 1,     
    SPI_CLK_1MHZ   = 2,     
    SPI_CLK_5MHZ   = 3,     
    SPI_CLK_10MHZ  = 4      
} spi_clk_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    uint8_t cpsr;           
    uint8_t scr;            
} spi_clk_conf_t;
 
#ifndef BOARD_HAS_SPI_CLK_CONF
 
static const spi_clk_conf_t spi_clk_config[] = {
    { .cpsr = 64, .scr =  4 },  /* 100khz */
    { .cpsr = 16, .scr =  4 },  /* 400khz */
    { .cpsr = 32, .scr =  0 },  /* 1.0MHz */
    { .cpsr =  2, .scr =  2 },  /* 5.3MHz */
    { .cpsr =  2, .scr =  1 }   /* 8.0MHz */
};
#endif /* BOARD_HAS_SPI_CLK_CONF */
 
typedef struct {
    uint8_t num;            
    gpio_t mosi_pin;        
    gpio_t miso_pin;        
    gpio_t sck_pin;         
    gpio_t cs_pin;          
} spi_conf_t;
typedef struct {
    uint_fast8_t chn;   
    uint_fast8_t cfg;   
} timer_conf_t;
 
#ifndef DOXYGEN
 
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  =             (0xa00),    
    ADC_RES_7BIT  =             (0 << 4),   
    ADC_RES_8BIT  =             (0xb00),    
    ADC_RES_9BIT  =             (1 << 4),   
    ADC_RES_10BIT =             (2 << 4),   
    ADC_RES_12BIT =             (3 << 4),   
    ADC_RES_14BIT =             (0xc00),    
    ADC_RES_16BIT =             (0xd00),    
} adc_res_t;
#endif /* ndef DOXYGEN */
 
typedef gpio_t adc_conf_t;
 
#define SOC_ADC_ADCCON3_EREF_INT      (0 << SOC_ADC_ADCCON3_EREF_S)    
#define SOC_ADC_ADCCON3_EREF_EXT      (1 << SOC_ADC_ADCCON3_EREF_S)    
#define SOC_ADC_ADCCON3_EREF_AVDD5    (2 << SOC_ADC_ADCCON3_EREF_S)    
#define SOC_ADC_ADCCON3_EREF_DIFF     (3 << SOC_ADC_ADCCON3_EREF_S)    
#define SOCADC_7_BIT_RSHIFT     (9U) 
#define SOCADC_9_BIT_RSHIFT     (7U) 
#define SOCADC_10_BIT_RSHIFT    (6U) 
#define SOCADC_12_BIT_RSHIFT    (4U) 
#define RTT_DEV             SMWDTHROSC
#define RTT_IRQ             SM_TIMER_ALT_IRQn
#define RTT_IRQ_PRIO        1
#define RTT_ISR             isr_sleepmode
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_FREQUENCY       (CLOCK_OSC32K)
/* When setting a new compare value, the value must be at least 5 more
   than the current sleep timer value. Otherwise, the timer compare
   event may be lost. */
#define RTT_MIN_OFFSET      (5U)
 
/* Limits are in clock cycles according to data sheet.
   As the WDT is clocked by a 32 kHz clock and supports 4 intervals */
#define NWDT_TIME_LOWER_LIMIT          (2U)
#define NWDT_TIME_UPPER_LIMIT          (1000U)
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */