periph_cpu.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <limits.h>
25 
26 #include "cpu.h"
27 #include "macros/units.h"
28 
29 #if defined(CPU_FAM_STM32F0)
30 #include "periph/f0/periph_cpu.h"
31 #elif defined(CPU_FAM_STM32F1)
32 #include "periph/f1/periph_cpu.h"
33 #elif defined(CPU_FAM_STM32F2)
34 #include "periph/f2/periph_cpu.h"
35 #elif defined(CPU_FAM_STM32F3)
36 #include "periph/f3/periph_cpu.h"
37 #elif defined(CPU_FAM_STM32F4)
38 #include "periph/f4/periph_cpu.h"
39 #elif defined(CPU_FAM_STM32F7)
40 #include "periph/f7/periph_cpu.h"
41 #elif defined(CPU_FAM_STM32G0)
42 #include "periph/g0/periph_cpu.h"
43 #elif defined(CPU_FAM_STM32G4)
44 #include "periph/g4/periph_cpu.h"
45 #elif defined(CPU_FAM_STM32L0)
46 #include "periph/l0/periph_cpu.h"
47 #elif defined(CPU_FAM_STM32L1)
48 #include "periph/l1/periph_cpu.h"
49 #elif defined(CPU_FAM_STM32L4)
50 #include "periph/l4/periph_cpu.h"
51 #elif defined(CPU_FAM_STM32L5)
52 #include "periph/l5/periph_cpu.h"
53 #elif defined(CPU_FAM_STM32WB)
54 #include "periph/wb/periph_cpu.h"
55 #endif
56 
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60 
64 #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F1) || \
65  defined(CPU_FAM_STM32F3)
66 #define CLOCK_LSI (40000U)
67 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
68 #define CLOCK_LSI (37000U)
69 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
70  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
71  defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
72  defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
73  defined(CPU_FAM_STM32MP1)
74 #define CLOCK_LSI (32000U)
75 #else
76 #error "error: LSI clock speed not defined for your target CPU"
77 #endif
78 
79 #ifdef Doxygen
80 
84 #define STM32_BOOTLOADER_ADDR
85 #endif
86 
92 #define CPUID_LEN (12U)
93 
97 #ifndef CPUID_ADDR
98 #define CPUID_ADDR (UID_BASE)
99 #endif
100 
104 #define PROVIDES_PM_LAYERED_OFF
105 
109 #define TIMER_CHANNEL_NUMOF (4U)
110 
114 #define TIM_CHAN(tim, chan) *(&dev(tim)->CCR1 + chan)
115 
119 #define QDEC_CHAN (2U)
120 
125 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
126 #define PERIPH_SPI_NEEDS_TRANSFER_REG
127 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
128 
137 #define PM_NUM_MODES (2U)
138 
143 #define STM32_PM_STOP (1U)
144 #define STM32_PM_STANDBY (0U)
145 
147 #ifndef PM_EWUP_CONFIG
148 
151 #define PM_EWUP_CONFIG (0U)
152 #endif
153 
159 /* Actual Lower Limit is ~100us so round up */
160 #define NWDT_TIME_LOWER_LIMIT (1U)
161 #define NWDT_TIME_UPPER_LIMIT (4U * US_PER_MS * 4096U * (1 << 6U) \
162  / CLOCK_LSI)
163 /* Once enabled wdt can't be stopped */
164 #define WDT_HAS_STOP (0U)
165 #if defined(CPU_FAM_STM32L4)
166 #define WDT_HAS_INIT (1U)
167 #else
168 #define WDT_HAS_INIT (0U)
169 #endif
170 
175 typedef enum {
176  APB1,
177  APB2,
178 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
179  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
180  defined(CPU_FAM_STM32L5)
181  APB12,
182 #endif
183 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32G0)
184  AHB,
185  IOP,
186 #elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) || \
187  defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
188  AHB,
189 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
190  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7) || \
191  defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
192  defined(CPU_FAM_STM32L5)
193  AHB1,
194  AHB2,
195  AHB3,
196 #elif defined(CPU_FAM_STM32MP1)
197  AHB1,
198  AHB2,
199  AHB3,
200 #else
201 #warning "unsupported stm32XX family"
202 #endif
203 #if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32MP1)
204  AHB4,
205 #endif
206 } bus_t;
207 
208 #ifndef DOXYGEN
209 
213 #define HAVE_GPIO_T
214 typedef uint32_t gpio_t;
216 #endif
217 
221 #define GPIO_UNDEF (0xffffffff)
222 
226 #if defined(CPU_FAM_STM32MP1)
227 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 12)) | y)
228 #else
229 #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y)
230 #endif
231 
235 enum {
236 #ifdef GPIOA
237  PORT_A = 0,
238 #endif
239 #ifdef GPIOB
240  PORT_B = 1,
241 #endif
242 #ifdef GPIOC
243  PORT_C = 2,
244 #endif
245 #ifdef GPIOD
246  PORT_D = 3,
247 #endif
248 #ifdef GPIOE
249  PORT_E = 4,
250 #endif
251 #ifdef GPIOF
252  PORT_F = 5,
253 #endif
254 #ifdef GPIOG
255  PORT_G = 6,
256 #endif
257 #ifdef GPIOH
258  PORT_H = 7,
259 #endif
260 #ifdef GPIOI
261  PORT_I = 8,
262 #endif
263 #ifdef GPIOJ
264  PORT_J = 9,
265 #endif
266 #ifdef GPIOK
267  PORT_K = 10,
268 #endif
269 };
270 
277 #define SPI_HWCS_MASK (0xffffff00)
278 
285 #define SPI_HWCS(x) (SPI_HWCS_MASK | x)
286 
292 #define PERIPH_I2C_NEED_READ_REG
293 
294 #define PERIPH_I2C_NEED_WRITE_REG
295 #define PERIPH_I2C_NEED_READ_REGS
296 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
297  defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F4) || \
298  defined(CPU_FAM_STM32MP1)
299 #define PERIPH_I2C_NEED_WRITE_REGS
300 #endif
301 
306 typedef enum {
307 #ifdef CPU_FAM_STM32F1
308  GPIO_AF_OUT_PP = 0xb,
309  GPIO_AF_OUT_OD = 0xf,
310 #else
311  GPIO_AF0 = 0,
312  GPIO_AF1,
313  GPIO_AF2,
314  GPIO_AF3,
315  GPIO_AF4,
316  GPIO_AF5,
317  GPIO_AF6,
318  GPIO_AF7,
319 #ifndef CPU_FAM_STM32F0
320  GPIO_AF8,
321  GPIO_AF9,
322  GPIO_AF10,
323  GPIO_AF11,
324  GPIO_AF12,
325  GPIO_AF13,
326  GPIO_AF14,
327  GPIO_AF15
328 #endif
329 #endif
330 } gpio_af_t;
331 
332 #ifdef CPU_FAM_STM32F1
333 #ifndef DOXYGEN
334 
343 #define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4))
344 
351 #define HAVE_GPIO_MODE_T
352 typedef enum {
353  GPIO_IN = GPIO_MODE(0, 1, 0),
354  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
355  GPIO_IN_PU = GPIO_MODE(0, 2, 1),
356  GPIO_OUT = GPIO_MODE(3, 0, 0),
357  GPIO_OD = GPIO_MODE(3, 1, 0),
358  GPIO_OD_PU = (0xff)
359 } gpio_mode_t;
361 #endif /* ndef DOXYGEN */
362 
367 #define HAVE_GPIO_PP_T
368 typedef enum {
369  GPIO_NOPULL = 4,
370  GPIO_PULLUP = 9,
371  GPIO_PULLDOWN = 8
372 } gpio_pp_t;
374 #else /* CPU_FAM_STM32F1 */
375 
383 #define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4))
384 
385 #ifndef DOXYGEN
386 
390 #define HAVE_GPIO_MODE_T
391 typedef enum {
392  GPIO_IN = GPIO_MODE(0, 0, 0),
393  GPIO_IN_PD = GPIO_MODE(0, 2, 0),
394  GPIO_IN_PU = GPIO_MODE(0, 1, 0),
395  GPIO_OUT = GPIO_MODE(1, 0, 0),
396  GPIO_OD = GPIO_MODE(1, 0, 1),
397  GPIO_OD_PU = GPIO_MODE(1, 1, 1)
398 } gpio_mode_t;
400 #endif /* ndef DOXYGEN */
401 #endif /* ndef CPU_FAM_STM32F1 */
402 
403 #ifndef DOXYGEN
404 
408 #define HAVE_GPIO_FLANK_T
409 typedef enum {
410  GPIO_RISING = 1,
411  GPIO_FALLING = 2,
412  GPIO_BOTH = 3
413 } gpio_flank_t;
415 #endif /* ndef DOXYGEN */
416 
420 typedef struct {
443  int stream;
444 } dma_conf_t;
445 
449 typedef unsigned dma_t;
450 
454 typedef enum {
455  DMA_PERIPH_TO_MEM = 0,
456  DMA_MEM_TO_PERIPH = 1,
457  DMA_MEM_TO_MEM = 2,
458 } dma_mode_t;
459 
464 #define DMA_CHAN_CONFIG_UNSUPPORTED (UINT8_MAX)
465 
470 #define DMA_INC_SRC_ADDR (0x04)
471 #define DMA_INC_DST_ADDR (0x08)
472 #define DMA_INC_BOTH_ADDR (DMA_INC_SRC_ADDR | DMA_INC_DST_ADDR)
473 
479 #define DMA_DATA_WIDTH_BYTE (0x00)
480 #define DMA_DATA_WIDTH_HALF_WORD (0x01)
481 #define DMA_DATA_WIDTH_WORD (0x02)
482 #define DMA_DATA_WIDTH_MASK (0x03)
483 #define DMA_DATA_WIDTH_SHIFT (0)
484 
489 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2)
490 #define ADC_DEVS (2U)
491 #elif defined(CPU_LINE_STM32F401xE) || defined(CPU_LINE_STM32F410Rx) \
492  || defined(CPU_LINE_STM32F411xE) || defined(CPU_LINE_STM32F412Zx) \
493  || defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx) \
494  || defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L432KC)
495 #define ADC_DEVS (1U)
496 #elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) \
497  || defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F429xx) \
498  || defined(CPU_LINE_STM32F437xx) || defined(CPU_LINE_STM32F446xx) \
499  || defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG)
500 #define ADC_DEVS (3U)
501 #endif
502 
506 typedef struct {
507  gpio_t pin;
508 #if !defined(CPU_FAM_STM32F0) && !defined(CPU_FAM_STM32L0) && \
509  !defined(CPU_FAM_STM32L1)
510  uint8_t dev;
511 #endif
512  uint8_t chan;
513 } adc_conf_t;
514 
518 typedef struct {
519  gpio_t pin;
520  uint8_t chan;
521 } dac_conf_t;
522 
526 typedef struct {
527  TIM_TypeDef *dev;
528  uint32_t max;
529  uint32_t rcc_mask;
530  uint8_t bus;
531  uint8_t irqn;
532 } timer_conf_t;
533 
537 typedef struct {
538  gpio_t pin;
539  uint8_t cc_chan;
540 } pwm_chan_t;
541 
545 typedef struct {
546  TIM_TypeDef *dev;
547  uint32_t rcc_mask;
548  pwm_chan_t chan[TIMER_CHANNEL_NUMOF];
551  gpio_af_t af;
552  uint8_t bus;
553 } pwm_conf_t;
554 
558 typedef struct {
559  gpio_t pin;
560  uint8_t cc_chan;
561 } qdec_chan_t;
562 
566 typedef struct {
567  TIM_TypeDef *dev;
568  uint32_t max;
569  uint32_t rcc_mask;
570  qdec_chan_t chan[QDEC_CHAN];
572 #ifndef CPU_FAM_STM32F1
573  gpio_af_t af;
574 #endif
575  uint8_t bus;
576  uint8_t irqn;
577 } qdec_conf_t;
578 
582 typedef enum {
583  STM32_USART,
584  STM32_LPUART,
585 } uart_type_t;
586 
590 #ifndef UART_TXBUF_SIZE
591 #define UART_TXBUF_SIZE (64)
592 #endif
593 
594 #ifndef DOXYGEN
595 
601 #define UART_INVALID_MODE (0x8000000)
602 
607 #define HAVE_UART_PARITY_T
608 typedef enum {
609  UART_PARITY_NONE = 0,
610  UART_PARITY_EVEN = USART_CR1_PCE,
611  UART_PARITY_ODD = (USART_CR1_PCE | USART_CR1_PS),
612  UART_PARITY_MARK = UART_INVALID_MODE | 4,
613  UART_PARITY_SPACE = UART_INVALID_MODE | 5
614 } uart_parity_t;
621 #define HAVE_UART_DATA_BITS_T
622 typedef enum {
623  UART_DATA_BITS_5 = UART_INVALID_MODE | 1,
624  UART_DATA_BITS_6 = UART_INVALID_MODE | 2,
625 #if defined(USART_CR1_M1)
626  UART_DATA_BITS_7 = USART_CR1_M1,
627 #else
628  UART_DATA_BITS_7 = UART_INVALID_MODE | 3,
629 #endif
630  UART_DATA_BITS_8 = 0,
631 } uart_data_bits_t;
638 #define HAVE_UART_STOP_BITS_T
639 typedef enum {
640  UART_STOP_BITS_1 = 0,
641  UART_STOP_BITS_2 = USART_CR2_STOP_1,
642 } uart_stop_bits_t;
644 #endif /* ndef DOXYGEN */
645 
650 #define HAVE_SPI_CLK_T
651 enum {
652  SPI_CLK_100KHZ = KHZ(100),
653  SPI_CLK_400KHZ = KHZ(400),
654  SPI_CLK_1MHZ = MHZ(1),
655  SPI_CLK_5MHZ = MHZ(5),
656  SPI_CLK_10MHZ = MHZ(10),
657 };
658 
662 typedef uint32_t spi_clk_t;
668 typedef struct {
669  USART_TypeDef *dev;
670  uint32_t rcc_mask;
671  gpio_t rx_pin;
672  gpio_t tx_pin;
673 #ifndef CPU_FAM_STM32F1
674  gpio_af_t rx_af;
675  gpio_af_t tx_af;
676 #endif
677  uint8_t bus;
678  uint8_t irqn;
679 #ifdef MODULE_PERIPH_UART_HW_FC
680  gpio_t cts_pin;
681  gpio_t rts_pin;
682 #ifndef CPU_FAM_STM32F1
683  gpio_af_t cts_af;
684  gpio_af_t rts_af;
685 #endif
686 #endif
687 #if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
688  defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
689  defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32MP1)
690  uart_type_t type;
691  uint32_t clk_src;
692 #endif
693 #ifdef MODULE_PERIPH_DMA
694  dma_t dma;
695  uint8_t dma_chan;
696 #endif
697 } uart_conf_t;
698 
702 typedef struct {
703  SPI_TypeDef *dev;
704  gpio_t mosi_pin;
705  gpio_t miso_pin;
706  gpio_t sclk_pin;
707  gpio_t cs_pin;
708 #ifndef CPU_FAM_STM32F1
709  gpio_af_t mosi_af;
710  gpio_af_t miso_af;
711  gpio_af_t sclk_af;
712  gpio_af_t cs_af;
713 #endif
714  uint32_t rccmask;
715  uint8_t apbbus;
716 #ifdef MODULE_PERIPH_DMA
717  dma_t tx_dma;
718  uint8_t tx_dma_chan;
719  dma_t rx_dma;
720  uint8_t rx_dma_chan;
721 #endif
722 } spi_conf_t;
723 
724 #ifndef DOXYGEN
725 
729 #define HAVE_I2C_SPEED_T
730 typedef enum {
731 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
732  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \
733  defined(CPU_FAM_STM32MP1)
734  I2C_SPEED_LOW,
735 #endif
736  I2C_SPEED_NORMAL,
737  I2C_SPEED_FAST,
738 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
739  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
740  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
741  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
742  defined(CPU_FAM_STM32L5)
743  I2C_SPEED_FAST_PLUS,
744 #endif
745 } i2c_speed_t;
747 #endif /* ndef DOXYGEN */
748 
752 typedef struct {
753  I2C_TypeDef *dev;
754  i2c_speed_t speed;
755  gpio_t scl_pin;
756  gpio_t sda_pin;
757 #ifndef CPU_FAM_STM32F1
758  gpio_af_t scl_af;
759  gpio_af_t sda_af;
760 #endif
761  uint8_t bus;
762  uint32_t rcc_mask;
763 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
764  uint32_t rcc_sw_mask;
765 #endif
766 #if defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) || \
767  defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32L1) || \
768  defined(CPU_FAM_STM32MP1)
769  uint32_t clk;
770 #endif
771  uint8_t irqn;
772 } i2c_conf_t;
773 
774 #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
775  defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
776  defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
777  defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
778  defined(CPU_FAM_STM32L5)
779 
790 typedef struct {
791  uint8_t presc;
792  uint8_t scll;
793  uint8_t sclh;
794  uint8_t sdadel;
795  uint8_t scldel;
796 } i2c_timing_param_t;
797 #endif
798 
808 typedef enum {
809  STM32_USB_OTG_FS = 0,
810  STM32_USB_OTG_HS = 1,
811 } stm32_usb_otg_fshs_type_t;
812 
819 typedef enum {
820  STM32_USB_OTG_PHY_BUILTIN,
821  STM32_USB_OTG_PHY_ULPI,
822 } stm32_usb_otg_fshs_phy_t;
823 
827 typedef struct {
828  uint8_t *periph;
829  uint32_t rcc_mask;
830  stm32_usb_otg_fshs_phy_t phy;
831  stm32_usb_otg_fshs_type_t type;
832  uint8_t irqn;
833  uint8_t ahb;
834  gpio_t dm;
835  gpio_t dp;
836  gpio_af_t af;
837 } stm32_usb_otg_fshs_config_t;
838 
846 uint32_t periph_apb_clk(uint8_t bus);
847 
855 uint32_t periph_timer_clk(uint8_t bus);
856 
863 void periph_clk_en(bus_t bus, uint32_t mask);
864 
871 void periph_lpclk_dis(bus_t bus, uint32_t mask);
872 
879 void periph_lpclk_en(bus_t bus, uint32_t mask);
880 
887 void periph_clk_dis(bus_t bus, uint32_t mask);
888 
895 void gpio_init_af(gpio_t pin, gpio_af_t af);
896 
902 void gpio_init_analog(gpio_t pin);
903 
904 #ifdef MODULE_PERIPH_DMA
905 
908 #define DMA_STREAM_UNDEF (UINT_MAX)
909 
913 void dma_init(void);
914 
931 int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
932  dma_mode_t mode, uint8_t flags);
933 
939 void dma_acquire(dma_t dma);
940 
946 void dma_release(dma_t dma);
947 
956 void dma_start(dma_t dma);
957 
965 uint16_t dma_suspend(dma_t dma);
966 
973 void dma_resume(dma_t dma, uint16_t remaining);
974 
980 void dma_stop(dma_t dma);
981 
987 void dma_wait(dma_t dma);
988 
1002 int dma_configure(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
1003  dma_mode_t mode, uint8_t flags);
1004 
1019 void dma_setup(dma_t dma, int chan, void *periph_addr, dma_mode_t mode,
1020  uint8_t width, bool inc_periph);
1021 
1030 void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
1031 
1032 #endif /* MODULE_PERIPH_DMA */
1033 
1034 #ifdef MODULE_PERIPH_CAN
1035 #include "candev_stm32.h"
1036 #endif
1037 
1041 typedef enum {
1042  MII = 18,
1043  RMII = 9,
1044  SMI = 2,
1045 } eth_mode_t;
1046 
1050 typedef struct {
1051  eth_mode_t mode;
1052  uint8_t addr[6];
1053  uint16_t speed;
1054  uint8_t dma;
1055  uint8_t dma_chan;
1056  uint8_t phy_addr;
1057  gpio_t pins[];
1060 } eth_conf_t;
1061 
1069 typedef struct eth_dma_desc {
1070  volatile uint32_t status;
1071  volatile uint32_t control;
1072  char * volatile buffer_addr;
1073  struct eth_dma_desc * volatile desc_next;
1074  volatile uint32_t reserved1_ext;
1075  volatile uint32_t reserved2;
1088  volatile uint32_t ts_low;
1089  volatile uint32_t ts_high;
1090 } edma_desc_t;
1091 
1096 #define RX_DESC_STAT_LS (BIT8)
1097 #define RX_DESC_STAT_FS (BIT9)
1104 #define RX_DESC_STAT_FL (0x3FFF0000) /* bits 16-29 */
1105 #define RX_DESC_STAT_DE (BIT14)
1106 #define RX_DESC_STAT_ES (BIT14)
1107 #define RX_DESC_STAT_OWN (BIT31)
1120 #define RX_DESC_CTRL_RCH (BIT14)
1121 
1126 #define TX_DESC_STAT_UF (BIT1)
1127 #define TX_DESC_STAT_EC (BIT8)
1128 #define TX_DESC_STAT_NC (BIT10)
1129 #define TX_DESC_STAT_ES (BIT15)
1130 #define TX_DESC_STAT_TTSS (BIT17)
1138 #define TX_DESC_STAT_TCH (BIT20)
1139 #define TX_DESC_STAT_TER (BIT21)
1150 #define TX_DESC_STAT_CIC (BIT22 | BIT23)
1151 #define TX_DESC_STAT_TTSE (BIT25)
1152 #define TX_DESC_STAT_FS (BIT28)
1153 #define TX_DESC_STAT_LS (BIT29)
1154 #define TX_DESC_STAT_IC (BIT30)
1155 #define TX_DESC_STAT_OWN (BIT31)
1158 #ifdef __cplusplus
1159 }
1160 #endif
1161 
1162 #endif /* PERIPH_CPU_H */
1163 
STM32_USB_OTG_HS
@ STM32_USB_OTG_HS
High speed peripheral.
Definition: periph_cpu.h:810
eth_dma_desc
Layout of enhanced RX/TX DMA descriptor.
Definition: periph_cpu.h:1069
SPI_CLK_400KHZ
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:653
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: periph_cpu.h:315
UART_PARITY_NONE
@ UART_PARITY_NONE
no parity
Definition: uart.h:127
GPIO_AF12
@ GPIO_AF12
use alternate function 12
Definition: periph_cpu.h:324
UART_DATA_BITS_5
@ UART_DATA_BITS_5
5 data bits
Definition: uart.h:140
gpio_init_analog
void gpio_init_analog(gpio_t pin)
Configure the given pin to be used as ADC input.
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
KHZ
#define KHZ(x)
A macro to return the Hz in x kHz.
Definition: units.h:44
stm32_usb_otg_fshs_config_t::irqn
uint8_t irqn
IRQ channel.
Definition: periph_cpu.h:832
eth_dma_desc::reserved2
volatile uint32_t reserved2
Reserved for future use.
Definition: periph_cpu.h:1075
uart_conf_t::dev
USART_TypeDef * dev
UART device base register address.
Definition: periph_cpu.h:669
SPI_CLK_100KHZ
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:652
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
timer_conf_t::rcc_mask
uint32_t rcc_mask
corresponding bit in the RCC register
Definition: periph_cpu.h:529
SMI
@ SMI
Configuration for SMI.
Definition: periph_cpu.h:1044
GPIO_AF13
@ GPIO_AF13
use alternate function 13
Definition: periph_cpu.h:325
i2c_conf_t::sda_af
gpio_af_t sda_af
sda pin alternate function value
Definition: periph_cpu.h:759
uart_stop_bits_t
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:151
I2C_SPEED_LOW
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition: i2c.h:176
candev_stm32.h
bxCAN specific definitions
dma_t
unsigned dma_t
DMA channel type.
Definition: periph_cpu_common.h:873
dac_conf_t::pin
gpio_t pin
pin connected to the line
Definition: periph_cpu.h:519
periph_lpclk_en
void periph_lpclk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock in low power mode.
GPIO_IN_PD
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
periph_cpu.h
STM32G0 CPU specific definitions for internal peripheral handling.
UART_STOP_BITS_2
@ UART_STOP_BITS_2
2 stop bits
Definition: uart.h:153
TIMER_CHANNEL_NUMOF
#define TIMER_CHANNEL_NUMOF
All STM timers have 4 capture-compare channels.
Definition: periph_cpu.h:109
eth_conf_t::phy_addr
uint8_t phy_addr
PHY address.
Definition: periph_cpu.h:1056
GPIO_OD
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
GPIO_AF15
@ GPIO_AF15
use alternate function 15
Definition: periph_cpu.h:327
periph_clk_en
void periph_clk_en(bus_t bus, uint32_t mask)
Enable the given peripheral clock.
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
spi_conf_t::rccmask
uint32_t rccmask
bit in the RCC peripheral enable register
Definition: periph_cpu.h:714
periph_cpu.h
STM32F3 CPU specific definitions for internal peripheral handling.
spi_conf_t::sclk_pin
gpio_t sclk_pin
SCLK pin.
Definition: periph_cpu.h:706
UART_DATA_BITS_8
@ UART_DATA_BITS_8
8 data bits
Definition: uart.h:143
gpio_af_t
gpio_af_t
Available MUX values for configuring a pin's alternate function.
Definition: periph_cpu_common.h:85
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
qdec_conf_t::rcc_mask
uint32_t rcc_mask
bit in clock enable register
Definition: periph_cpu.h:569
pwm_conf_t::dev
TIM_TypeDef * dev
Timer used.
Definition: periph_cpu.h:546
periph_cpu.h
STM3G4 CPU specific definitions for internal peripheral handling.
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
timer_conf_t::dev
TIM_TypeDef * dev
timer device
Definition: periph_cpu.h:527
i2c_conf_t::irqn
uint8_t irqn
I2C event interrupt number.
Definition: periph_cpu.h:771
qdec_chan_t
QDEC channel.
Definition: periph_cpu.h:558
stm32_usb_otg_fshs_config_t::af
gpio_af_t af
Alternative function.
Definition: periph_cpu.h:836
dac_conf_t::chan
uint8_t chan
DAC device used for this line.
Definition: periph_cpu.h:520
i2c_conf_t::scl_af
gpio_af_t scl_af
scl pin alternate function value
Definition: periph_cpu.h:758
stm32_usb_otg_fshs_config_t::dm
gpio_t dm
Data- gpio.
Definition: periph_cpu.h:834
bus_t
bus_t
Available peripheral buses.
Definition: periph_cpu.h:175
GPIO_OUT
@ GPIO_OUT
configure as output in push-pull mode
Definition: gpio.h:122
pwm_chan_t::pin
gpio_t pin
GPIO pin mapped to this channel.
Definition: periph_cpu.h:538
spi_conf_t::sclk_af
gpio_af_t sclk_af
SCLK pin alternate function.
Definition: periph_cpu.h:711
dma_wait
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
stm32_usb_otg_fshs_config_t::phy
stm32_usb_otg_fshs_phy_t phy
Built-in or ULPI phy.
Definition: periph_cpu.h:830
GPIO_AF6
@ GPIO_AF6
use alternate function 6
Definition: periph_cpu.h:317
UART_DATA_BITS_6
@ UART_DATA_BITS_6
6 data bits
Definition: uart.h:141
stm32_usb_otg_fshs_config_t::dp
gpio_t dp
Data+ gpio.
Definition: periph_cpu.h:835
uart_parity_t
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:126
i2c_speed_t
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:175
eth_dma_desc::ts_low
volatile uint32_t ts_low
Sub-second part of PTP timestamp of transmitted / sent frame.
Definition: periph_cpu.h:1088
i2c_conf_t::bus
uint8_t bus
APB bus.
Definition: periph_cpu.h:761
i2c_conf_t::rcc_mask
uint32_t rcc_mask
bit in clock enable register
Definition: periph_cpu.h:762
periph_clk_dis
void periph_clk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock in low power mode.
pwm_chan_t::cc_chan
uint8_t cc_chan
capture compare channel used
Definition: periph_cpu.h:539
GPIO_FALLING
@ GPIO_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:81
pwm_conf_t::rcc_mask
uint32_t rcc_mask
bit in clock enable register
Definition: periph_cpu.h:547
adc_conf_t::dev
uint8_t dev
ADCx - 1 device used for the channel.
Definition: periph_cpu.h:510
stm32_usb_otg_fshs_config_t::type
stm32_usb_otg_fshs_type_t type
FS or HS type.
Definition: periph_cpu.h:831
periph_cpu.h
STM32L0 CPU specific definitions for internal peripheral handling.
periph_timer_clk
uint32_t periph_timer_clk(uint8_t bus)
Get the actual timer clock frequency.
QDEC_CHAN
#define QDEC_CHAN
All STM QDEC timers have 2 capture channels.
Definition: periph_cpu.h:119
GPIO_IN_PU
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
eth_conf_t::dma_chan
uint8_t dma_chan
DMA channel used for TX.
Definition: periph_cpu.h:1055
GPIO_RISING
@ GPIO_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:82
dma_init
void dma_init(void)
Initialize DMA.
dma_conf_t::stream
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: periph_cpu.h:443
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
dma_mode_t
dma_mode_t
DMA modes.
Definition: periph_cpu.h:454
eth_dma_desc::status
volatile uint32_t status
Mostly status bits, some control bits.
Definition: periph_cpu.h:1070
SPI_CLK_10MHZ
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:656
spi_clk_t
uint32_t spi_clk_t
SPI clock type.
Definition: periph_cpu.h:662
GPIO_IN
@ GPIO_IN
configure as input without pull resistor
Definition: gpio.h:119
GPIO_AF3
@ GPIO_AF3
use alternate function 3
Definition: periph_cpu.h:314
stm32_usb_otg_fshs_type_t
stm32_usb_otg_fshs_type_t
USB OTG peripheral type.
Definition: periph_cpu.h:808
qdec_conf_t::dev
TIM_TypeDef * dev
Timer used.
Definition: periph_cpu.h:567
eth_conf_t::mode
eth_mode_t mode
Select configuration mode.
Definition: periph_cpu.h:1051
periph_cpu.h
STM32L4 CPU specific definitions for internal peripheral handling.
stm32_usb_otg_fshs_config_t::periph
uint8_t * periph
USB peripheral base address.
Definition: periph_cpu.h:828
qdec_chan_t::pin
gpio_t pin
GPIO pin mapped to this channel.
Definition: periph_cpu.h:559
dma_start
void dma_start(dma_t dma)
Start a DMA transfer.
periph_cpu.h
STM32F0 CPU specific definitions for internal peripheral handling.
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
DMA_PERIPH_TO_MEM
@ DMA_PERIPH_TO_MEM
Peripheral to memory.
Definition: periph_cpu.h:455
PORT_F
@ PORT_F
port F
Definition: periph_cpu.h:41
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition: periph_cpu.h:583
spi_conf_t::mosi_af
gpio_af_t mosi_af
MOSI pin alternate function.
Definition: periph_cpu.h:709
timer_conf_t::bus
uint8_t bus
APBx bus the timer is clock from.
Definition: periph_cpu.h:530
qdec_conf_t::max
uint32_t max
Maximum counter value.
Definition: periph_cpu.h:568
GPIO_AF14
@ GPIO_AF14
use alternate function 14
Definition: periph_cpu.h:326
edma_desc_t
struct eth_dma_desc edma_desc_t
Layout of enhanced RX/TX DMA descriptor.
SPI_CLK_5MHZ
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:655
GPIO_MODE
#define GPIO_MODE(io, pr, ot)
Generate GPIO mode bitfields.
Definition: periph_cpu.h:383
pwm_chan_t
PWM channel.
Definition: periph_cpu.h:537
gpio_flank_t
gpio_flank_t
Definition: periph_cpu.h:80
dac_conf_t
DAC line configuration data.
Definition: periph_cpu.h:518
GPIO_OD_PU
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
UART_PARITY_SPACE
@ UART_PARITY_SPACE
space parity
Definition: uart.h:131
DMA_MEM_TO_MEM
@ DMA_MEM_TO_MEM
Memory to memory.
Definition: periph_cpu.h:457
pwm_conf_t::af
gpio_af_t af
alternate function used
Definition: periph_cpu.h:551
gpio_af_t
gpio_af_t
Available MUX values for configuring a pin's alternate function.
Definition: periph_cpu.h:306
eth_dma_desc::reserved1_ext
volatile uint32_t reserved1_ext
RX: Extended status, TX: reserved.
Definition: periph_cpu.h:1074
periph_cpu.h
STM32F4 CPU specific definitions for internal peripheral handling.
eth_mode_t
eth_mode_t
STM32 Ethernet configuration mode.
Definition: periph_cpu.h:1041
spi_conf_t::miso_af
gpio_af_t miso_af
MISO pin alternate function.
Definition: periph_cpu.h:710
stm32_usb_otg_fshs_config_t::rcc_mask
uint32_t rcc_mask
bit in clock enable register
Definition: periph_cpu.h:829
stm32_usb_otg_fshs_config_t
stm32 USB OTG configuration
Definition: periph_cpu.h:827
DMA_MEM_TO_PERIPH
@ DMA_MEM_TO_PERIPH
Memory to peripheral.
Definition: periph_cpu.h:456
gpio_init_af
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
Configure an alternate function for the given pin.
eth_conf_t::dma
uint8_t dma
Locical CMA Descriptor used for TX.
Definition: periph_cpu.h:1054
dma_setup
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
dma_t
unsigned dma_t
DMA type.
Definition: periph_cpu.h:449
eth_dma_desc::control
volatile uint32_t control
Control bits.
Definition: periph_cpu.h:1071
GPIO_BOTH
@ GPIO_BOTH
emit interrupt on both flanks
Definition: periph_cpu.h:83
GPIO_AF9
@ GPIO_AF9
use alternate function 9
Definition: periph_cpu.h:321
qdec_conf_t::irqn
uint8_t irqn
global IRQ channel
Definition: periph_cpu.h:576
UART_PARITY_EVEN
@ UART_PARITY_EVEN
even parity
Definition: uart.h:128
qdec_conf_t::bus
uint8_t bus
APB bus.
Definition: periph_cpu.h:575
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
periph_apb_clk
uint32_t periph_apb_clk(uint8_t bus)
Get the actual bus clock frequency for the APB buses.
adc_conf_t
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:315
units.h
Unit helper macros.
eth_conf_t
Ethernet Peripheral configuration.
Definition: periph_cpu.h:1050
STM32_USB_OTG_FS
@ STM32_USB_OTG_FS
Full speed peripheral.
Definition: periph_cpu.h:809
dma_prepare
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
spi_conf_t::cs_af
gpio_af_t cs_af
HWCS pin alternate function.
Definition: periph_cpu.h:712
spi_conf_t::dev
SPI_TypeDef * dev
SPI device base register address.
Definition: periph_cpu.h:703
RMII
@ RMII
Configuration for RMII.
Definition: periph_cpu.h:1043
stm32_usb_otg_fshs_phy_t
stm32_usb_otg_fshs_phy_t
Type of USB OTG peripheral phy.
Definition: periph_cpu.h:819
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
GPIO_AF11
@ GPIO_AF11
use alternate function 11
Definition: periph_cpu.h:323
uart_conf_t::rcc_mask
uint32_t rcc_mask
bit in clock enable register
Definition: periph_cpu.h:670
stm32_usb_otg_fshs_config_t::ahb
uint8_t ahb
AHB bus.
Definition: periph_cpu.h:833
eth_conf_t::speed
uint16_t speed
Speed selection.
Definition: periph_cpu.h:1053
gpio_mode_t
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:70
UART_DATA_BITS_7
@ UART_DATA_BITS_7
7 data bits
Definition: uart.h:142
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu.h:320
eth_dma_desc::buffer_addr
char *volatile buffer_addr
RX/TX buffer.
Definition: periph_cpu.h:1072
qdec_conf_t
QDEC configuration.
Definition: periph_cpu.h:566
periph_cpu.h
STM32F2 CPU specific definitions for internal peripheral handling.
eth_dma_desc::ts_high
volatile uint32_t ts_high
Second part of PTP timestamp.
Definition: periph_cpu.h:1089
GPIO_AF10
@ GPIO_AF10
use alternate function 10
Definition: periph_cpu.h:322
periph_cpu.h
STM32WB CPU specific definitions for internal peripheral handling.
periph_lpclk_dis
void periph_lpclk_dis(bus_t bus, uint32_t mask)
Disable the given peripheral clock.
dma_conf_t
DMA configuration.
Definition: periph_cpu.h:420
PORT_K
@ PORT_K
port K
Definition: periph_cpu.h:43
MII
@ MII
Configuration for MII.
Definition: periph_cpu.h:1042
periph_cpu.h
STM32L1 CPU specific definitions for internal peripheral handling.
periph_cpu.h
STM32F7 CPU specific definitions for internal peripheral handling.
spi_conf_t::apbbus
uint8_t apbbus
APBx bus the device is connected to.
Definition: periph_cpu.h:715
eth_dma_desc::desc_next
struct eth_dma_desc *volatile desc_next
Address of next DMA descriptor.
Definition: periph_cpu.h:1073
UART_PARITY_MARK
@ UART_PARITY_MARK
mark parity
Definition: uart.h:130
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu.h:316
UART_STOP_BITS_1
@ UART_STOP_BITS_1
1 stop bit
Definition: uart.h:152
uart_data_bits_t
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:139
qdec_conf_t::af
gpio_af_t af
alternate function used
Definition: periph_cpu.h:573
UART_PARITY_ODD
@ UART_PARITY_ODD
odd parity
Definition: uart.h:129
PORT_H
@ PORT_H
port H
Definition: periph_cpu.h:41
STM32_LPUART
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: periph_cpu.h:584
gpio_t
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu.h:318
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu.h:312
I2C_SPEED_FAST_PLUS
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition: i2c.h:179
uart_type_t
uart_type_t
UART hardware module types.
Definition: periph_cpu.h:506
SPI_CLK_1MHZ
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:654
I2C_SPEED_FAST
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: i2c.h:178
periph_cpu.h
STM32L5 CPU specific definitions for internal peripheral handling.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
PORT_J
@ PORT_J
port J
Definition: periph_cpu.h:42
periph_cpu.h
STM32F1 CPU specific definitions for internal peripheral handling.
PORT_G
@ PORT_G
port G
Definition: periph_cpu.h:42
qdec_chan_t::cc_chan
uint8_t cc_chan
capture compare channel used
Definition: periph_cpu.h:560
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
MHZ
#define MHZ(x)
A macro to return the Hz in x MHz.
Definition: units.h:49
pwm_conf_t::bus
uint8_t bus
APB bus.
Definition: periph_cpu.h:552
GPIO_AF0
@ GPIO_AF0
use alternate function 0
Definition: periph_cpu.h:311
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176
uart_conf_t::bus
uint8_t bus
APB bus.
Definition: periph_cpu.h:677
GPIO_AF2
@ GPIO_AF2
use alternate function 2
Definition: periph_cpu.h:313