periph_cpu_common.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CPU_COMMON_H
22 #define PERIPH_CPU_COMMON_H
23 
24 #include "cpu.h"
25 #include "exti_config.h"
26 #include "timer_config.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
35 #define CPUID_LEN (16U)
36 
41 #define PERIPH_SPI_NEEDS_INIT_CS
42 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
43 #ifndef MODULE_PERIPH_DMA
44 #define PERIPH_SPI_NEEDS_TRANSFER_REG
45 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
46 #endif
47 
53 #define PERIPH_I2C_NEED_READ_REG
54 #define PERIPH_I2C_NEED_READ_REGS
55 #define PERIPH_I2C_NEED_WRITE_REG
56 #define PERIPH_I2C_NEED_WRITE_REGS
57 
63 #define HAVE_GPIO_T
64 typedef uint32_t gpio_t;
70 #define GPIO_UNDEF (0xffffffff)
71 
76 #ifdef CPU_FAM_SAML11
77 #define GPIO_PIN(x, y) (((gpio_t)(&PORT_SEC->Group[x])) | y)
78 #elif defined(PORT_IOBUS) /* Use IOBUS access when available */
79 #define GPIO_PIN(x, y) (((gpio_t)(&PORT_IOBUS->Group[x])) | y)
80 #else
81 #define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
82 #endif
83 
87 enum {
88  PA = 0,
89  PB = 1,
90  PC = 2,
91  PD = 3,
92 };
93 
102 #define GPIO_MODE(pr, ie, pe) (pr | (ie << 1) | (pe << 2))
103 
104 #ifndef DOXYGEN
105 
108 #define HAVE_GPIO_MODE_T
109 typedef enum {
110  GPIO_IN = GPIO_MODE(0, 1, 0),
111  GPIO_IN_PD = GPIO_MODE(0, 1, 1),
112  GPIO_IN_PU = GPIO_MODE(1, 1, 1),
113  GPIO_OUT = GPIO_MODE(0, 0, 0),
114  GPIO_OD = 0xfe,
115  GPIO_OD_PU = 0xff
116 } gpio_mode_t;
117 
122 #define HAVE_GPIO_FLANK_T
123 typedef enum {
124  GPIO_FALLING = 2,
125  GPIO_RISING = 1,
126  GPIO_BOTH = 3
127 } gpio_flank_t;
129 #endif /* ndef DOXYGEN */
130 
134 #ifndef SAM_MUX_T
135 typedef enum {
136  GPIO_MUX_A = 0x0,
137  GPIO_MUX_B = 0x1,
138  GPIO_MUX_C = 0x2,
139  GPIO_MUX_D = 0x3,
140  GPIO_MUX_E = 0x4,
141  GPIO_MUX_F = 0x5,
142  GPIO_MUX_G = 0x6,
143  GPIO_MUX_H = 0x7,
144 } gpio_mux_t;
145 #endif
146 
150 typedef enum {
151  UART_PAD_RX_0 = 0x0,
152  UART_PAD_RX_1 = 0x1,
153  UART_PAD_RX_2 = 0x2,
154  UART_PAD_RX_3 = 0x3,
155 } uart_rxpad_t;
156 
160 typedef enum {
161  UART_PAD_TX_0 = 0x0,
162  UART_PAD_TX_2 = 0x1,
163  UART_PAD_TX_0_RTS_2_CTS_3 = 0x2,
165 } uart_txpad_t;
166 
170 typedef enum {
171  UART_FLAG_NONE = 0x0,
172  UART_FLAG_RUN_STANDBY = 0x1,
173  UART_FLAG_WAKEUP = 0x2,
174  UART_FLAG_RXINV = 0x4,
175  UART_FLAG_TXINV = 0x8,
176 } uart_flag_t;
177 
178 #ifndef DOXYGEN
179 
186 #define HAVE_UART_DATA_BITS_T
187 typedef enum {
188  UART_DATA_BITS_5 = 0x5,
189  UART_DATA_BITS_6 = 0x6,
190  UART_DATA_BITS_7 = 0x7,
191  UART_DATA_BITS_8 = 0x0,
192 } uart_data_bits_t;
199 #define uart_pin_rx(dev) uart_config[dev].rx_pin
200 #define uart_pin_tx(dev) uart_config[dev].tx_pin
201 
203 #endif /* ndef DOXYGEN */
204 
205 
209 #ifndef UART_TXBUF_SIZE
210 #define UART_TXBUF_SIZE (64)
211 #endif
212 
226 typedef struct {
227  SercomUsart *dev;
228  gpio_t rx_pin;
229  gpio_t tx_pin;
230 #ifdef MODULE_PERIPH_UART_HW_FC
231  gpio_t rts_pin;
232  gpio_t cts_pin;
233 #endif
234  gpio_mux_t mux;
235  uart_rxpad_t rx_pad;
236  uart_txpad_t tx_pad;
237  uart_flag_t flags;
238  uint8_t gclk_src;
239 } uart_conf_t;
240 
241 enum {
242  TIMER_TYPE_TC,
243  TIMER_TYPE_TCC,
244 };
245 
249 typedef struct {
250  union {
251 #ifdef REV_TC
252  Tc *tc;
253 #endif
254 #ifdef REV_TCC
255  Tcc *tcc;
256 #endif
257  } dev;
258 #ifdef MCLK
259  volatile uint32_t *mclk;
260  uint32_t mclk_mask;
261 #else
262  uint32_t pm_mask;
263 #endif
264  uint16_t gclk_id;
265  uint8_t type;
266 } tc_tcc_cfg_t;
267 
271 #ifdef MCLK
272 #define TC_CONFIG(tim) { \
273  .dev = {.tc = tim}, \
274  .mclk = MCLK_ ## tim, \
275  .mclk_mask = MCLK_ ## tim ## _MASK, \
276  .gclk_id = tim ## _GCLK_ID, \
277  .type = TIMER_TYPE_TC, }
278 #else
279 #define TC_CONFIG(tim) { \
280  .dev = {.tc = tim}, \
281  .pm_mask = PM_APBCMASK_ ## tim, \
282  .gclk_id = tim ## _GCLK_ID, \
283  .type = TIMER_TYPE_TC, }
284 #endif
285 
289 #ifdef MCLK
290 #define TCC_CONFIG(tim) { \
291  .dev = {.tcc = tim}, \
292  .mclk = MCLK_ ## tim, \
293  .mclk_mask = MCLK_ ## tim ## _MASK, \
294  .gclk_id = tim ## _GCLK_ID, \
295  .type = TIMER_TYPE_TCC, }
296 #else
297 #define TCC_CONFIG(tim) { \
298  .dev = {.tcc = tim}, \
299  .pm_mask = PM_APBCMASK_ ## tim, \
300  .gclk_id = tim ## _GCLK_ID, \
301  .type = TIMER_TYPE_TCC, }
302 #endif
303 
307 typedef struct {
308  gpio_t pin;
309  gpio_mux_t mux;
310  uint8_t chan;
311 } pwm_conf_chan_t;
312 
316 typedef struct {
317  tc_tcc_cfg_t tim;
318  const pwm_conf_chan_t *chan;
319  uint8_t chan_numof;
320  uint8_t gclk_src;
321 } pwm_conf_t;
322 
326 typedef enum {
327  SPI_PAD_MISO_0 = 0x0,
328  SPI_PAD_MISO_1 = 0x1,
329  SPI_PAD_MISO_2 = 0x2,
330  SPI_PAD_MISO_3 = 0x3,
331 } spi_misopad_t;
332 
336 typedef enum {
337  SPI_PAD_MOSI_0_SCK_1 = 0x0,
338  SPI_PAD_MOSI_2_SCK_3 = 0x1,
339  SPI_PAD_MOSI_3_SCK_1 = 0x2,
340  SPI_PAD_MOSI_0_SCK_3 = 0x3,
341 } spi_mosipad_t;
342 
343 #ifndef DOXYGEN
344 
348 #define HAVE_SPI_MODE_T
349 typedef enum {
350  SPI_MODE_0 = 0x0,
351  SPI_MODE_1 = 0x1,
352  SPI_MODE_2 = 0x2,
353  SPI_MODE_3 = 0x3
354 } spi_mode_t;
361 #define HAVE_SPI_CLK_T
362 typedef enum {
363  SPI_CLK_100KHZ = 100000U,
364  SPI_CLK_400KHZ = 400000U,
365  SPI_CLK_1MHZ = 1000000U,
366  SPI_CLK_5MHZ = 5000000U,
367  SPI_CLK_10MHZ = 10000000U
368 } spi_clk_t;
375 #define spi_pin_mosi(dev) spi_config[dev].mosi_pin
376 #define spi_pin_miso(dev) spi_config[dev].miso_pin
377 #define spi_pin_clk(dev) spi_config[dev].clk_pin
378 
380 #endif /* ndef DOXYGEN */
381 
385 typedef struct {
386  SercomSpi *dev;
387  gpio_t miso_pin;
388  gpio_t mosi_pin;
389  gpio_t clk_pin;
390  gpio_mux_t miso_mux;
391  gpio_mux_t mosi_mux;
392  gpio_mux_t clk_mux;
393  spi_misopad_t miso_pad;
394  spi_mosipad_t mosi_pad;
395  uint8_t gclk_src;
396 #ifdef MODULE_PERIPH_DMA
397  uint8_t tx_trigger;
398  uint8_t rx_trigger;
399 #endif
400 } spi_conf_t;
406 typedef enum {
407  I2C_FLAG_NONE = 0x0,
408  I2C_FLAG_RUN_STANDBY = 0x1,
409 } i2c_flag_t;
410 
411 #ifndef DOXYGEN
412 
416 #define HAVE_I2C_SPEED_T
417 typedef enum {
418  I2C_SPEED_LOW = 10000U,
419  I2C_SPEED_NORMAL = 100000U,
420  I2C_SPEED_FAST = 400000U,
421  I2C_SPEED_FAST_PLUS = 1000000U,
422  I2C_SPEED_HIGH = 3400000U,
423 } i2c_speed_t;
430 #define i2c_pin_sda(dev) i2c_config[dev].sda_pin
431 #define i2c_pin_scl(dev) i2c_config[dev].scl_pin
432 
434 #endif /* ndef DOXYGEN */
435 
448 typedef struct {
449  SercomI2cm *dev;
450  i2c_speed_t speed;
451  gpio_t scl_pin;
452  gpio_t sda_pin;
453  gpio_mux_t mux;
454  uint8_t gclk_src;
455  uint8_t flags;
456 } i2c_conf_t;
457 
461 typedef struct {
462  Tc *dev;
463  IRQn_Type irq;
464 #ifdef MCLK
465  volatile uint32_t *mclk;
466  uint32_t mclk_mask;
467  uint16_t gclk_id;
468 #else
469  uint32_t pm_mask;
470  uint16_t gclk_ctrl;
471 #endif
472  uint8_t gclk_src;
473  uint16_t flags;
474 } tc32_conf_t;
475 
479 #define TIMER_CHANNEL_NUMOF (2)
480 
487 void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
488 
494 void gpio_pm_cb_enter(int deep);
495 
501 void gpio_pm_cb_leave(int deep);
502 
508 void cpu_pm_cb_enter(int deep);
509 
515 void cpu_pm_cb_leave(int deep);
516 
522 static inline void sam0_cortexm_sleep(int deep)
523 {
524 #ifdef MODULE_PERIPH_GPIO
525  gpio_pm_cb_enter(deep);
526 #endif
527 
528  cpu_pm_cb_enter(deep);
529 
530  cortexm_sleep(deep);
531 
532  cpu_pm_cb_leave(deep);
533 
534 #ifdef MODULE_PERIPH_GPIO
535  gpio_pm_cb_leave(deep);
536 #endif
537 }
538 
544 void gpio_disable_mux(gpio_t pin);
545 
549 typedef enum {
550  SAM0_VREG_LDO, /*< LDO, always available but not very power efficient */
551  SAM0_VREG_BUCK /*< Buck converter, efficient but may clash with internal
552  fast clock generators (see errata sheets) */
553 } sam0_supc_t;
554 
568 static inline void sam0_set_voltage_regulator(sam0_supc_t src)
569 {
570 #ifdef REG_SUPC_VREG
571  SUPC->VREG.bit.SEL = src;
572  while (!SUPC->STATUS.bit.VREGRDY) {}
573 #else
574  (void) src;
575  assert(0);
576 #endif
577 }
578 
586 uint32_t sam0_gclk_freq(uint8_t id);
587 
593 void sam0_gclk_enable(uint8_t id);
594 
602 static inline uint8_t sercom_id(const void *sercom)
603 {
604 #ifdef SERCOM0
605  if (sercom == SERCOM0) {
606  return 0;
607  }
608 #endif
609 #ifdef SERCOM1
610  if (sercom == SERCOM1) {
611  return 1;
612  }
613 #endif
614 #ifdef SERCOM2
615  if (sercom == SERCOM2) {
616  return 2;
617  }
618 #endif
619 #ifdef SERCOM3
620  if (sercom == SERCOM3) {
621  return 3;
622  }
623 #endif
624 #ifdef SERCOM4
625  if (sercom == SERCOM4) {
626  return 4;
627  }
628 #endif
629 #ifdef SERCOM5
630  if (sercom == SERCOM5) {
631  return 5;
632  }
633 #endif
634 #ifdef SERCOM6
635  if (sercom == SERCOM6) {
636  return 6;
637  }
638 #endif
639 #ifdef SERCOM7
640  if (sercom == SERCOM7) {
641  return 7;
642  }
643 #endif
644 
645  /* should not be reached, so fail with assert */
646  assert(false);
647 
648  return SERCOM_INST_NUM;
649 }
650 
656 static inline void sercom_clk_en(void *sercom)
657 {
658  const uint8_t id = sercom_id(sercom);
659 #if defined(CPU_COMMON_SAMD21)
660  PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << id);
661 #elif defined (CPU_COMMON_SAMD5X)
662  if (id < 2) {
663  MCLK->APBAMASK.reg |= (1 << (id + 12));
664  } else if (id < 4) {
665  MCLK->APBBMASK.reg |= (1 << (id + 7));
666  } else {
667  MCLK->APBDMASK.reg |= (1 << (id - 4));
668  }
669 #else
670  if (id < 5) {
671  MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << id);
672  }
673 #if defined(CPU_COMMON_SAML21)
674  else {
675  MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
676  }
677 #endif /* CPU_COMMON_SAML21 */
678 #endif
679 }
680 
686 static inline void sercom_clk_dis(void *sercom)
687 {
688  const uint8_t id = sercom_id(sercom);
689 #if defined(CPU_COMMON_SAMD21)
690  PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << id);
691 #elif defined (CPU_COMMON_SAMD5X)
692  if (id < 2) {
693  MCLK->APBAMASK.reg &= ~(1 << (id + 12));
694  } else if (id < 4) {
695  MCLK->APBBMASK.reg &= ~(1 << (id + 7));
696  } else {
697  MCLK->APBDMASK.reg &= ~(1 << (id - 4));
698  }
699 #else
700  if (id < 5) {
701  MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << id);
702  }
703 #if defined (CPU_COMMON_SAML21)
704  else {
705  MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
706  }
707 #endif /* CPU_COMMON_SAML21 */
708 #endif
709 }
710 
711 #ifdef CPU_COMMON_SAMD5X
712 static inline uint8_t _sercom_gclk_id_core(uint8_t sercom_id) {
713  if (sercom_id < 2)
714  return sercom_id + 7;
715  if (sercom_id < 4)
716  return sercom_id + 21;
717  else
718  return sercom_id + 30;
719 }
720 #endif
721 
728 static inline void sercom_set_gen(void *sercom, uint8_t gclk)
729 {
730  const uint8_t id = sercom_id(sercom);
731  sam0_gclk_enable(gclk);
732 #if defined(CPU_COMMON_SAMD21)
733  GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(gclk) |
734  (SERCOM0_GCLK_ID_CORE + id));
735  while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
736 #elif defined(CPU_COMMON_SAMD5X)
737  GCLK->PCHCTRL[_sercom_gclk_id_core(id)].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
738 #else
739  if (id < 5) {
740  GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + id].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
741  }
742 #if defined(CPU_COMMON_SAML21)
743  else {
744  GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = (GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(gclk));
745  }
746 #endif /* CPU_COMMON_SAML21 */
747 #endif
748 }
749 
753 static inline bool cpu_woke_from_backup(void)
754 {
755 #ifdef RSTC_RCAUSE_BACKUP
756  return RSTC->RCAUSE.bit.BACKUP;
757 #else
758  return false;
759 #endif
760 }
761 
765 typedef struct {
766  gpio_t pin;
767  uint32_t muxpos;
768 } adc_conf_chan_t;
769 
773 #if defined(USB_INST_NUM) || defined(DOXYGEN)
774 typedef struct {
775  gpio_t dm;
776  gpio_t dp;
777  gpio_mux_t d_mux;
778  UsbDevice *device;
779  uint8_t gclk_src;
780 } sam0_common_usb_config_t;
781 #endif /* USB_INST_NUM */
782 
787 /* Limits are in clock cycles according to data sheet.
788  As the WDT is clocked by a 1024 Hz clock, 1 cycle ≈ 1 ms */
789 #define NWDT_TIME_LOWER_LIMIT (8U)
790 #define NWDT_TIME_UPPER_LIMIT (16384U)
791 
797 #define WDT_HAS_STOP (1)
798 
801 #define WDT_HAS_INIT (1)
802 
852 #define DMA_TRIGGER_DISABLED 0
853 
857 #if defined(CPU_COMMON_SAML21) || defined(DOXYGEN)
858 #define DMA_DESCRIPTOR_IN_LPSRAM
859 #endif
860 
864 #ifdef DMA_DESCRIPTOR_IN_LPSRAM
865 #define DMA_DESCRIPTOR_ATTRS __attribute__((section(".backup.bss")))
866 #else
867 #define DMA_DESCRIPTOR_ATTRS
868 #endif
869 
873 typedef unsigned dma_t;
874 
878 typedef enum {
879  DMA_INCR_NONE = 0,
880  DMA_INCR_SRC = 1,
881  DMA_INCR_DEST = 2,
882  DMA_INCR_BOTH = 3,
883 } dma_incr_t;
884 
888 void dma_init(void);
889 
900 dma_t dma_acquire_channel(void);
901 
907 void dma_release_channel(dma_t dma);
908 
917 void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq);
918 
932 void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst,
933  size_t num, dma_incr_t incr);
934 
955 void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr);
956 
977 void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr);
978 
998 void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width,
999  const void *src, void *dst, size_t num, dma_incr_t incr);
1000 
1019 void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src,
1020  size_t num, bool incr);
1021 
1040 void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num,
1041  bool incr);
1042 
1048 void dma_start(dma_t dma);
1049 
1059 void dma_wait(dma_t dma);
1060 
1069 void dma_cancel(dma_t dma);
1080 void rtc_tamper_init(void);
1081 
1090 int rtc_tamper_register(gpio_t pin, gpio_flank_t flank);
1091 
1095 void rtc_tamper_enable(void);
1112 typedef struct sam0_aux_cfg_mapping nvm_user_page_t;
1113 
1117 #ifdef FLASH_USER_PAGE_SIZE
1118 #define FLASH_USER_PAGE_AUX_SIZE (FLASH_USER_PAGE_SIZE - sizeof(nvm_user_page_t))
1119 #else
1120 #define FLASH_USER_PAGE_AUX_SIZE (AUX_PAGE_SIZE * AUX_NB_OF_PAGES - sizeof(nvm_user_page_t))
1121 #endif
1122 
1131 void sam0_flashpage_aux_reset(const nvm_user_page_t *cfg);
1132 
1148 void sam0_flashpage_aux_write(uint32_t offset, const void *data, size_t len);
1149 
1157 #define sam0_flashpage_aux_get(offset) \
1158  (const void*)((uint8_t*)NVMCTRL_USER + sizeof(nvm_user_page_t) + (offset))
1159 
1165 #define sam0_flashpage_aux_cfg() \
1166  ((const nvm_user_page_t*)NVMCTRL_USER)
1167 
1170 #ifdef __cplusplus
1171 }
1172 #endif
1173 
1174 #endif /* PERIPH_CPU_COMMON_H */
1175 
spi_misopad_t
spi_misopad_t
Available values for SERCOM SPI MISO pad selection.
Definition: periph_cpu_common.h:326
dma_append
void dma_append(dma_t dma, DmacDescriptor *descriptor, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Append a second transfer descriptor after the default channel descriptor.
tc_tcc_cfg_t::gclk_id
uint16_t gclk_id
TCn_GCLK_ID.
Definition: periph_cpu_common.h:264
sam0_cortexm_sleep
static void sam0_cortexm_sleep(int deep)
Wrapper for cortexm_sleep calling power management callbacks.
Definition: periph_cpu_common.h:522
SPI_CLK_400KHZ
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:653
tc32_conf_t::gclk_ctrl
uint16_t gclk_ctrl
GCLK_CLKCTRL_ID for the Timer.
Definition: periph_cpu_common.h:470
sam0_flashpage_aux_write
void sam0_flashpage_aux_write(uint32_t offset, const void *data, size_t len)
Write data to the user configuration area.
SPI_MODE_3
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition: spi.h:161
adc_conf_chan_t::muxpos
uint32_t muxpos
ADC channel pin multiplexer value.
Definition: periph_cpu_common.h:767
UART_DATA_BITS_5
@ UART_DATA_BITS_5
5 data bits
Definition: uart.h:140
GPIO_MUX_F
@ GPIO_MUX_F
select peripheral function F
Definition: periph_cpu_common.h:141
rtc_tamper_register
int rtc_tamper_register(gpio_t pin, gpio_flank_t flank)
Enable Tamper Detection IRQs.
PD
@ PD
port D
Definition: periph_cpu_common.h:91
spi_conf_t::dev
SercomSpi * dev
pointer to the used SPI device
Definition: periph_cpu_common.h:386
pwm_conf_chan_t::pin
gpio_t pin
GPIO pin.
Definition: periph_cpu_common.h:308
SPI_CLK_100KHZ
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:652
sam0_gclk_freq
uint32_t sam0_gclk_freq(uint8_t id)
Returns the frequency of a GCLK provider.
sam0_supc_t
sam0_supc_t
Available voltage regulators on the supply controller.
Definition: periph_cpu_common.h:549
spi_conf_t::gclk_src
uint8_t gclk_src
GCLK source which supplys SERCOM.
Definition: periph_cpu_common.h:395
UART_PAD_RX_3
@ UART_PAD_RX_3
select pad 3
Definition: periph_cpu_common.h:154
spi_conf_t::clk_mux
gpio_mux_t clk_mux
alternate function for CLK pin (mux)
Definition: periph_cpu_common.h:392
dma_incr_t
dma_incr_t
Available DMA address increment modes.
Definition: periph_cpu_common.h:878
uart_conf_t::flags
uart_flag_t flags
set optional SERCOM flags
Definition: periph_cpu_common.h:237
UART_PAD_TX_0_RTS_2_CTS_3
@ UART_PAD_TX_0_RTS_2_CTS_3
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
Definition: periph_cpu_common.h:163
dma_prepare_dst
void dma_prepare_dst(dma_t dma, void *dst, size_t num, bool incr)
Prepare a transfer without modifying the source address settings.
sam0_common_usb_config_t::dp
gpio_t dp
D+ line gpio
Definition: periph_cpu_common.h:776
sam0_common_usb_config_t::d_mux
gpio_mux_t d_mux
alternate function (mux) for data pins
Definition: periph_cpu_common.h:777
dma_cancel
void dma_cancel(dma_t dma)
Cancel an active DMA transfer.
I2C_SPEED_LOW
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition: i2c.h:176
dma_t
unsigned dma_t
DMA channel type.
Definition: periph_cpu_common.h:873
pwm_conf_t::gclk_src
uint8_t gclk_src
GCLK source which clocks TIMER.
Definition: periph_cpu_common.h:320
uart_conf_t::dev
SercomUsart * dev
pointer to the used UART device
Definition: periph_cpu_common.h:227
dma_append_dst
void dma_append_dst(dma_t dma, DmacDescriptor *next, void *dst, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying source and block si...
GPIO_IN_PD
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
GPIO_MUX_E
@ GPIO_MUX_E
select peripheral function E
Definition: periph_cpu_common.h:140
sam0_aux_cfg_mapping
NVM User Row Mapping - Dedicated Entries Config values will be applied at power-on.
Definition: periph_cpu.h:130
assert
#define assert(cond)
abort the program if assertion is false
Definition: assert.h:104
tc_tcc_cfg_t
Common configuration for timer devices.
Definition: periph_cpu_common.h:249
rtc_tamper_init
void rtc_tamper_init(void)
Power on the RTC (if the RTC/RTT is not otherwise used)
SPI_MODE_0
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition: spi.h:158
GPIO_OD
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
UART_FLAG_TXINV
@ UART_FLAG_TXINV
invert TX signal
Definition: periph_cpu_common.h:175
IRQn_Type
enum IRQn IRQn_Type
Interrupt Number Definition.
UART_FLAG_WAKEUP
@ UART_FLAG_WAKEUP
wake from sleep on receive
Definition: periph_cpu_common.h:173
UART_DATA_BITS_8
@ UART_DATA_BITS_8
8 data bits
Definition: uart.h:143
UART_PAD_TX_0
@ UART_PAD_TX_0
select pad 0
Definition: periph_cpu_common.h:161
gpio_pm_cb_leave
void gpio_pm_cb_leave(int deep)
Called after the power management left a power mode.
I2C_FLAG_RUN_STANDBY
@ I2C_FLAG_RUN_STANDBY
run SERCOM in standby mode
Definition: periph_cpu_common.h:408
sam0_set_voltage_regulator
static void sam0_set_voltage_regulator(sam0_supc_t src)
Switch the internal voltage regulator used for generating the internal MCU voltages.
Definition: periph_cpu_common.h:568
uart_flag_t
uart_flag_t
Available SERCOM UART flag selections.
Definition: periph_cpu_common.h:170
uart_txpad_t
uart_txpad_t
Available values for SERCOM UART TX pad selection.
Definition: periph_cpu_common.h:160
I2C_FLAG_NONE
@ I2C_FLAG_NONE
No flags set.
Definition: periph_cpu_common.h:407
UART_FLAG_NONE
@ UART_FLAG_NONE
No flags set.
Definition: periph_cpu_common.h:171
GPIO_OUT
@ GPIO_OUT
configure as output in push-pull mode
Definition: gpio.h:122
UART_PAD_RX_0
@ UART_PAD_RX_0
use pad 0 for RX line
Definition: periph_cpu_common.h:151
dma_wait
void dma_wait(dma_t dma)
Wait for a DMA channel to finish the transfer.
SPI_PAD_MOSI_0_SCK_3
@ SPI_PAD_MOSI_0_SCK_3
use pad 0 for MOSI, pad 3 for SCK
Definition: periph_cpu_common.h:340
TIMER_TYPE_TCC
@ TIMER_TYPE_TCC
Timer is a TCC timer.
Definition: periph_cpu_common.h:243
uart_conf_t::gclk_src
uint8_t gclk_src
GCLK source which supplys SERCOM.
Definition: periph_cpu_common.h:238
UART_DATA_BITS_6
@ UART_DATA_BITS_6
6 data bits
Definition: uart.h:141
PB
@ PB
port B
Definition: periph_cpu_common.h:89
rtc_tamper_enable
void rtc_tamper_enable(void)
Enable Tamper Detection IRQs.
i2c_speed_t
i2c_speed_t
Default mapping of I2C bus speed values.
Definition: i2c.h:175
spi_mode_t
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
pwm_conf_t::chan_numof
uint8_t chan_numof
number of channels
Definition: periph_cpu_common.h:319
uart_conf_t::rx_pad
uart_rxpad_t rx_pad
pad selection for RX line
Definition: periph_cpu_common.h:235
DMA_INCR_NONE
@ DMA_INCR_NONE
Don't increment any addresses after a beat.
Definition: periph_cpu_common.h:879
UART_FLAG_RXINV
@ UART_FLAG_RXINV
invert RX signal
Definition: periph_cpu_common.h:174
sam0_common_usb_config_t
USB peripheral parameters.
Definition: periph_cpu_common.h:774
dma_append_src
void dma_append_src(dma_t dma, DmacDescriptor *next, const void *src, size_t num, bool incr)
Append a second transfer descriptor after the default channel descriptor, copying destination and blo...
sam0_common_usb_config_t::dm
gpio_t dm
D- line gpio
Definition: periph_cpu_common.h:775
uart_conf_t::tx_pad
uart_txpad_t tx_pad
pad selection for TX line
Definition: periph_cpu_common.h:236
tc_tcc_cfg_t::type
uint8_t type
Timer type (TC/TCC)
Definition: periph_cpu_common.h:265
DMA_INCR_SRC
@ DMA_INCR_SRC
Increment the source address after a beat.
Definition: periph_cpu_common.h:880
GPIO_FALLING
@ GPIO_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:81
sam0_common_usb_config_t::gclk_src
uint8_t gclk_src
GCLK source which supplys 48 MHz
Definition: periph_cpu_common.h:779
i2c_conf_t::gclk_src
uint8_t gclk_src
GCLK source which supplys SERCOM.
Definition: periph_cpu_common.h:454
SPI_PAD_MISO_1
@ SPI_PAD_MISO_1
use pad 0 for MISO line
Definition: periph_cpu_common.h:328
sercom_set_gen
static void sercom_set_gen(void *sercom, uint8_t gclk)
Configure generator clock for given SERCOM device.
Definition: periph_cpu_common.h:728
gpio_init_mux
void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
Set up alternate function (PMUX setting) for a PORT pin.
dma_release_channel
void dma_release_channel(dma_t dma)
Release a previously acquired DMA channel.
i2c_conf_t::dev
SercomI2cm * dev
pointer to the used I2C device
Definition: periph_cpu_common.h:449
GPIO_IN_PU
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
GPIO_RISING
@ GPIO_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:82
dma_init
void dma_init(void)
Initialize DMA.
gpio_pm_cb_enter
void gpio_pm_cb_enter(int deep)
Called before the power management enters a power mode.
pwm_conf_t
PWM device configuration.
Definition: periph_cpu_common.h:153
UART_PAD_RX_1
@ UART_PAD_RX_1
select pad 1
Definition: periph_cpu_common.h:152
SPI_CLK_10MHZ
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:656
SPI_PAD_MISO_0
@ SPI_PAD_MISO_0
use pad 0 for MISO line
Definition: periph_cpu_common.h:327
GPIO_IN
@ GPIO_IN
configure as input without pull resistor
Definition: gpio.h:119
i2c_conf_t::flags
uint8_t flags
allow SERCOM to run in standby mode
Definition: periph_cpu_common.h:455
spi_clk_t
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
tc32_conf_t::pm_mask
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
Definition: periph_cpu_common.h:469
spi_conf_t::miso_pad
spi_misopad_t miso_pad
pad to use for MISO line
Definition: periph_cpu_common.h:393
pwm_conf_chan_t
PWM channel configuration data structure.
Definition: periph_cpu_common.h:307
tc32_conf_t::gclk_src
uint8_t gclk_src
GCLK source which supplys Timer.
Definition: periph_cpu_common.h:472
DMA_INCR_BOTH
@ DMA_INCR_BOTH
Increment both addresses after a beat.
Definition: periph_cpu_common.h:882
UART_PAD_TX_2
@ UART_PAD_TX_2
select pad 2
Definition: periph_cpu_common.h:162
dma_start
void dma_start(dma_t dma)
Start a DMA transfer.
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
cpu_pm_cb_enter
void cpu_pm_cb_enter(int deep)
Called before the power management enters a power mode.
gpio_disable_mux
void gpio_disable_mux(gpio_t pin)
Disable alternate function (PMUX setting) for a PORT pin.
gpio_mux_t
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
Definition: periph_cpu_common.h:135
spi_conf_t::mosi_pad
spi_mosipad_t mosi_pad
pad to use for MOSI and CLK line
Definition: periph_cpu_common.h:394
GPIO_MUX_A
@ GPIO_MUX_A
select peripheral function A
Definition: periph_cpu_common.h:136
uart_conf_t::mux
gpio_mux_t mux
alternative function for pins
Definition: periph_cpu_common.h:234
SPI_CLK_5MHZ
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:655
sam0_flashpage_aux_reset
void sam0_flashpage_aux_reset(const nvm_user_page_t *cfg)
Reset the configuration area, apply a new configuration.
gpio_flank_t
gpio_flank_t
Definition: periph_cpu.h:80
GPIO_MUX_B
@ GPIO_MUX_B
select peripheral function B
Definition: periph_cpu_common.h:137
spi_conf_t::mosi_mux
gpio_mux_t mosi_mux
alternate function for MOSI pin (mux)
Definition: periph_cpu_common.h:391
GPIO_OD_PU
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
cpu_woke_from_backup
static bool cpu_woke_from_backup(void)
Returns true if the CPU woke deep sleep (backup/standby)
Definition: periph_cpu_common.h:753
cpu_pm_cb_leave
void cpu_pm_cb_leave(int deep)
Called after the power management left a power mode.
spi_conf_t::miso_mux
gpio_mux_t miso_mux
alternate function for MISO pin (mux)
Definition: periph_cpu_common.h:390
uart_rxpad_t
uart_rxpad_t
Available values for SERCOM UART RX pad selection.
Definition: periph_cpu_common.h:150
UART_FLAG_RUN_STANDBY
@ UART_FLAG_RUN_STANDBY
run SERCOM in standby mode
Definition: periph_cpu_common.h:172
tc32_conf_t::dev
Tc * dev
pointer to the used Timer device
Definition: periph_cpu_common.h:462
GPIO_MUX_C
@ GPIO_MUX_C
select peripheral function C
Definition: periph_cpu_common.h:138
DMA_INCR_DEST
@ DMA_INCR_DEST
Increment destination address after a beat.
Definition: periph_cpu_common.h:881
dma_setup
void dma_setup(dma_t dma, unsigned trigger, uint8_t prio, bool irq)
Initialize a previously allocated DMA channel with one-time settings.
SPI_PAD_MOSI_0_SCK_1
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
Definition: periph_cpu_common.h:337
SPI_PAD_MOSI_2_SCK_3
@ SPI_PAD_MOSI_2_SCK_3
use pad 2 for MOSI, pad 3 for SCK
Definition: periph_cpu_common.h:338
GPIO_BOTH
@ GPIO_BOTH
emit interrupt on both flanks
Definition: periph_cpu.h:83
spi_mosipad_t
spi_mosipad_t
Available values for SERCOM SPI MOSI and SCK pad selection.
Definition: periph_cpu_common.h:336
dma_prepare
void dma_prepare(dma_t dma, uint8_t width, const void *src, void *dst, size_t num, dma_incr_t incr)
Prepare the DMA channel for an individual transfer.
spi_conf_t::clk_pin
gpio_t clk_pin
used CLK pin
Definition: periph_cpu_common.h:389
pwm_conf_chan_t::chan
uint8_t chan
TCC channel to use.
Definition: periph_cpu_common.h:310
sam0_gclk_enable
void sam0_gclk_enable(uint8_t id)
Enables an on-demand GCLK that has been configured in cpu.c.
adc_conf_chan_t
ADC Channel Configuration.
Definition: periph_cpu_common.h:765
tc32_conf_t
Timer device configuration.
Definition: periph_cpu_common.h:461
SPI_PAD_MISO_3
@ SPI_PAD_MISO_3
use pad 0 for MISO line
Definition: periph_cpu_common.h:330
TIMER_TYPE_TC
@ TIMER_TYPE_TC
Timer is a TC timer
Definition: periph_cpu_common.h:242
cortexm_sleep
static void cortexm_sleep(int deep)
Put the CPU into (deep) sleep mode, using the WFI instruction.
Definition: cpu.h:160
gpio_mode_t
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:70
sercom_id
static uint8_t sercom_id(const void *sercom)
Return the numeric id of a SERCOM device derived from its address.
Definition: periph_cpu_common.h:602
GPIO_MUX_D
@ GPIO_MUX_D
select peripheral function D
Definition: periph_cpu_common.h:139
UART_DATA_BITS_7
@ UART_DATA_BITS_7
7 data bits
Definition: uart.h:142
adc_conf_chan_t::pin
gpio_t pin
ADC channel pin.
Definition: periph_cpu_common.h:766
GPIO_MUX_H
@ GPIO_MUX_H
select peripheral function H
Definition: periph_cpu_common.h:143
PC
@ PC
port C
Definition: periph_cpu_common.h:90
pwm_conf_chan_t::mux
gpio_mux_t mux
pin function multiplex value
Definition: periph_cpu_common.h:309
PA
@ PA
port A
Definition: periph_cpu_common.h:88
uart_data_bits_t
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition: uart.h:139
tc32_conf_t::irq
IRQn_Type irq
IRQ# of Timer Interrupt.
Definition: periph_cpu_common.h:463
GPIO_MODE
#define GPIO_MODE(pr, ie, pe)
Generate GPIO mode bitfields.
Definition: periph_cpu_common.h:102
gpio_t
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
SPI_PAD_MOSI_3_SCK_1
@ SPI_PAD_MOSI_3_SCK_1
use pad 3 for MOSI, pad 1 for SCK
Definition: periph_cpu_common.h:339
SPI_PAD_MISO_2
@ SPI_PAD_MISO_2
use pad 0 for MISO line
Definition: periph_cpu_common.h:329
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
I2C_SPEED_FAST_PLUS
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition: i2c.h:179
dma_acquire_channel
dma_t dma_acquire_channel(void)
Acquire a DMA channel.
sercom_clk_en
static void sercom_clk_en(void *sercom)
Enable peripheral clock for given SERCOM device.
Definition: periph_cpu_common.h:656
tc32_conf_t::flags
uint16_t flags
flags for CTRA, e.g.
Definition: periph_cpu_common.h:473
GPIO_MUX_G
@ GPIO_MUX_G
select peripheral function G
Definition: periph_cpu_common.h:142
SPI_CLK_1MHZ
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:654
sercom_clk_dis
static void sercom_clk_dis(void *sercom)
Disable peripheral clock for given SERCOM device.
Definition: periph_cpu_common.h:686
I2C_SPEED_FAST
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: i2c.h:178
UART_PAD_RX_2
@ UART_PAD_RX_2
select pad 2
Definition: periph_cpu_common.h:153
dma_prepare_src
void dma_prepare_src(dma_t dma, const void *src, size_t num, bool incr)
Prepare a transfer without modifying the destination address settings.
pwm_conf_t::chan
const pwm_conf_chan_t * chan
channel configuration
Definition: periph_cpu_common.h:318
tc_tcc_cfg_t::pm_mask
uint32_t pm_mask
PM_APBCMASK bits to enable Timer.
Definition: periph_cpu_common.h:262
I2C_SPEED_HIGH
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition: i2c.h:180
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
SPI_MODE_1
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition: spi.h:159
sam0_common_usb_config_t::device
UsbDevice * device
ptr to the device registers
Definition: periph_cpu_common.h:778
i2c_flag_t
i2c_flag_t
Available SERCOM I2C flag selections.
Definition: periph_cpu_common.h:406
i2c_conf_t::mux
gpio_mux_t mux
alternate function (mux)
Definition: periph_cpu_common.h:453
SPI_MODE_2
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition: spi.h:160
pwm_conf_t::tim
tc_tcc_cfg_t tim
timer configuration
Definition: periph_cpu_common.h:317