periph_cpu.h

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/*
 * Copyright (C) 2015-2016 Freie Universität Berlin
 * Copyright (C) 2017-2018 Eistec AB
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <stdint.h>
#include <stdbool.h>
 
#include "cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#ifdef PORT_PCR_MUX
#  define KINETIS_HAVE_PCR
#endif
 
#ifdef SIM_PINSEL_REG
#  define KINETIS_HAVE_PINSEL
#endif
 
#ifdef ADC_CFG1_MODE_MASK
#  define KINETIS_HAVE_ADC_K
#endif
 
#ifdef SPI_CTAR_CPHA_MASK
#  define KINETIS_HAVE_MK_SPI
#endif
 
#ifdef LPTMR_CSR_TEN_MASK
#  define KINETIS_HAVE_LPTMR
#endif
 
#define HAVE_GPIO_T
typedef uint16_t gpio_t;
#define GPIO_UNDEF          (0xffff)
 
#define GPIO_PIN(x, y)      (((x + 1) << 12) | (x << 6) | y)
 
#ifdef SIM_UIDH_UID_MASK
/* Kinetis Cortex-M4 has a 128 bit SIM UID */
#define CPUID_ADDR          (&SIM->UIDH)
 
#define CPUID_LEN           (16U)
#else /* defined(SIM_UIDH_UID_MASK) */
/* Kinetis Cortex-M0+ has a 96 bit SIM UID */
#define CPUID_ADDR          (&SIM->UIDMH)
 
#define CPUID_LEN           (12U)
#endif /* defined(SIM_UIDH_UID_MASK) */
 
#define GPIO_MODE(pu, pe, od, out)   (pu | (pe << 1) | (od << 5) | (out << 7))
 
#define SPI_HWCS(x)         (x)
 
#define SPI_HWCS_NUMOF      (5)
 
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE  1
#define PERIPH_SPI_NEEDS_TRANSFER_REG   1
#define PERIPH_SPI_NEEDS_TRANSFER_REGS  1
 
#define PERIPH_TIMER_PROVIDES_SET
 
#define PM_NUM_MODES    (3U)
enum {
    KINETIS_PM_LLS  = 0,
    KINETIS_PM_VLPS = 1,
    KINETIS_PM_STOP = 2,
    KINETIS_PM_WAIT = 3,
};
#if MODULE_PM_LAYERED
#include "pm_layered.h"
#define PM_BLOCK(x) pm_block(x)
 
#define PM_UNBLOCK(x) pm_unblock(x)
#else
/* ignore these calls when not using pm_layered */
#define PM_BLOCK(x)
#define PM_UNBLOCK(x)
#endif
 
#ifdef RTC
/* All Kinetis CPUs have exactly one RTC hardware module, except for the KL02
 * family which don't have an RTC at all */
#define RTT_FREQUENCY                (1)
#define RTT_MAX_VALUE                (0xffffffff)
 
#endif
 
#ifndef DOXYGEN
 
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN    = GPIO_MODE(0, 0, 0, 0),     
    GPIO_IN_PD = GPIO_MODE(0, 1, 0, 0),     
    GPIO_IN_PU = GPIO_MODE(1, 1, 0, 0),     
    GPIO_OUT   = GPIO_MODE(0, 0, 0, 1),     
    GPIO_OD    = GPIO_MODE(1, 0, 1, 1),     
    GPIO_OD_PU = GPIO_MODE(1, 1, 1, 1),     
} gpio_mode_t;
#endif /* ndef DOXYGEN */
 
#ifdef KINETIS_HAVE_PCR
 
typedef enum {
    GPIO_AF_ANALOG = PORT_PCR_MUX(0),       
    GPIO_AF_GPIO   = PORT_PCR_MUX(1),       
    GPIO_AF_2      = PORT_PCR_MUX(2),       
    GPIO_AF_3      = PORT_PCR_MUX(3),       
    GPIO_AF_4      = PORT_PCR_MUX(4),       
    GPIO_AF_5      = PORT_PCR_MUX(5),       
    GPIO_AF_6      = PORT_PCR_MUX(6),       
    GPIO_AF_7      = PORT_PCR_MUX(7),       
#ifdef PORT_PCR_ODE_MASK
    GPIO_PCR_OD    = (PORT_PCR_ODE_MASK),   
#endif
    GPIO_PCR_PD    = (PORT_PCR_PE_MASK),    
    GPIO_PCR_PU    = (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)  
} gpio_pcr_t;
#endif /* KINETIS_HAVE_PCR */
 
#ifndef DOXYGEN
 
#ifdef KINETIS_HAVE_PCR
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_RISING  = PORT_PCR_IRQC(0x9),  
    GPIO_FALLING = PORT_PCR_IRQC(0xa),  
    GPIO_BOTH    = PORT_PCR_IRQC(0xb),  
} gpio_flank_t;
#endif /* KINETIS_HAVE_PCR */
 
#endif /* ndef DOXYGEN */
 
enum {
    PORT_A = 0,             
    PORT_B = 1,             
    PORT_C = 2,             
    PORT_D = 3,             
    PORT_E = 4,             
    PORT_F = 5,             
    PORT_G = 6,             
    GPIO_PORTS_NUMOF        
};
 
#ifndef DOXYGEN
 
#define HAVE_ADC_RES_T
#ifdef KINETIS_HAVE_ADC_K
typedef enum {
    ADC_RES_6BIT  = (0xfe),             
    ADC_RES_8BIT  = ADC_CFG1_MODE(0),   
    ADC_RES_10BIT = ADC_CFG1_MODE(2),   
    ADC_RES_12BIT = ADC_CFG1_MODE(1),   
    ADC_RES_14BIT = (0xff),             
    ADC_RES_16BIT = ADC_CFG1_MODE(3)    
} adc_res_t;
#endif /* KINETIS_HAVE_ADC_K */
 
#if defined(FTM_CnSC_MSB_MASK)
 
#define PWM_CHAN_MAX        (4U)
 
#define HAVE_PWM_MODE_T
typedef enum {
    PWM_LEFT   = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK),  
    PWM_RIGHT  = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK),  
    PWM_CENTER = (FTM_CnSC_MSB_MASK)                        
} pwm_mode_t;
#endif /* defined(FTM_CnSC_MSB_MASK) */
#endif /* ndef DOXYGEN */
 
typedef enum {
    UART_MODE_8N1 = 0,
#if defined(UART_C1_M_MASK) || DOXYGEN
    /* LPUART and UART mode bits coincide, so the same setting for UART works on
     * the LPUART as well */
    UART_MODE_8E1 = (UART_C1_M_MASK | UART_C1_PE_MASK),
#elif defined(LPUART_CTRL_M_MASK)
    /* For CPUs which only have the LPUART */
    UART_MODE_8E1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK),
#endif
#if defined(UART_C1_M_MASK) || DOXYGEN
    UART_MODE_8O1 = (UART_C1_M_MASK | UART_C1_PE_MASK | UART_C1_PT_MASK),
#elif defined(LPUART_CTRL_M_MASK)
    /* For CPUs which only have the LPUART */
    UART_MODE_8O1 = (LPUART_CTRL_M_MASK | LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK),
#endif
} uart_mode_t;
 
#ifndef DOXYGEN
 
#ifdef KINETIS_HAVE_MK_SPI
#define HAVE_SPI_MODE_T
typedef enum {
#if defined(SPI_CTAR_CPHA_MASK)
    SPI_MODE_0 = 0,                                         
    SPI_MODE_1 = (SPI_CTAR_CPHA_MASK),                      
    SPI_MODE_2 = (SPI_CTAR_CPOL_MASK),                      
    SPI_MODE_3 = (SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK)  
#elif defined(SPI_C1_CPHA_MASK)
    SPI_MODE_0 = 0,                                         
    SPI_MODE_1 = (SPI_C1_CPHA_MASK),                        
    SPI_MODE_2 = (SPI_C1_CPOL_MASK),                        
    SPI_MODE_3 = (SPI_C1_CPOL_MASK | SPI_C1_CPHA_MASK)      
#endif
} spi_mode_t;
#endif /* KINETIS_HAVE_MK_SPI */
#endif /* ndef DOXYGEN */
 
typedef struct {
    ADC_Type *dev;
    gpio_t pin;
    uint8_t chan;
    uint8_t avg;
} adc_conf_t;
 
#define ADC_AVG_NONE    (0)
 
#define ADC_AVG_MAX     (ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3))
 
#if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
 
typedef struct {
    DAC_Type *dev;                  
    volatile uint32_t *scgc_addr;   
    uint8_t scgc_bit;               
} dac_conf_t;
#endif
 
typedef struct {
    uint8_t prescaler_ch;
    uint8_t count_ch;
} pit_conf_t;
 
#ifdef KINETIS_HAVE_LPTMR
 
typedef struct {
    LPTMR_Type *dev;
    uint32_t base_freq;
    uint8_t src;
    uint8_t irqn;
} lptmr_conf_t;
#endif /* KINETIS_HAVE_LPTMR */
 
#ifdef FTM_CnSC_MSB_MASK
 
typedef struct {
    FTM_Type* ftm;          
    struct {
        gpio_t pin;         
        uint8_t af;         
        uint8_t ftm_chan;   
    } chan[PWM_CHAN_MAX];   
    uint8_t chan_numof;     
    uint8_t ftm_num;        
#ifdef KINETIS_HAVE_PINSEL
    volatile uint32_t *pinsel;
    uint32_t pinsel_mask;
    uint32_t pinsel_val;
#endif
} pwm_conf_t;
#endif
 
#ifndef DOXYGEN
#define HAVE_I2C_SPEED_T
typedef enum {
    I2C_SPEED_LOW       =   10000ul, 
    I2C_SPEED_NORMAL    =  100000ul, 
    I2C_SPEED_FAST      =  400000ul, 
    I2C_SPEED_FAST_PLUS = 1000000ul, 
    /* High speed is not supported without external hardware hacks */
    I2C_SPEED_HIGH      = 3400000ul, 
} i2c_speed_t;
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_WRITE_REGS
 
#endif /* !defined(DOXYGEN) */
 
typedef struct {
    I2C_Type *i2c;          
    gpio_t scl_pin;         
    gpio_t sda_pin;         
    uint32_t freq;          
    i2c_speed_t speed;      
    IRQn_Type irqn;         
    uint32_t scl_pcr;       
    uint32_t sda_pcr;       
} i2c_conf_t;
 
typedef struct {
    SPI_Type *dev;                      
    gpio_t pin_miso;                    
    gpio_t pin_mosi;                    
    gpio_t pin_clk;                     
    gpio_t pin_cs[SPI_HWCS_NUMOF];      
#ifdef KINETIS_HAVE_PCR
    gpio_pcr_t pcr;                     
#endif /* KINETIS_HAVE_PCR */
#ifdef KINETIS_HAVE_PINSEL
    volatile uint32_t *pinsel;
    uint32_t pinsel_mask;
    uint32_t pinsel_val;
#endif
    uint32_t simmask;                   
} spi_conf_t;
 
enum {
    TIMER_PIT,              
#ifdef KINETIS_HAVE_LPTMR
    TIMER_LPTMR,            
#endif /* KINETIS_HAVE_LPTMR */
};
 
#define TIMER_PIT_DEV(x)   (TIMER_DEV(0 + (x)))
#ifdef KINETIS_HAVE_LPTMR
 
#define TIMER_LPTMR_DEV(x) (TIMER_DEV(PIT_NUMOF + (x)))
#endif /* KINETIS_HAVE_LPTMR */
 
typedef enum {
    KINETIS_UART,   
    KINETIS_LPUART, 
} uart_type_t;
 
typedef struct {
    void *dev;                    
    uint32_t freq;                
    gpio_t pin_rx;                
    gpio_t pin_tx;                
#ifdef KINETIS_HAVE_PCR
    uint32_t pcr_rx;              
    uint32_t pcr_tx;              
#endif
#ifdef KINETIS_HAVE_PINSEL
    volatile uint32_t *pinsel;
    uint32_t pinsel_mask;
    uint32_t pinsel_val;
#endif
    IRQn_Type irqn;               
    volatile uint32_t *scgc_addr; 
    uint8_t scgc_bit;             
    uart_mode_t mode;             
    uart_type_t type;             
} uart_conf_t;
 
#if !defined(KINETIS_HAVE_PLL) && defined(MODULE_PERIPH_MCG) \
  && defined(MCG_C6_PLLS_MASK) || DOXYGEN
 
#define KINETIS_HAVE_PLL 1
#else
#define KINETIS_HAVE_PLL 0
#endif
 
#ifdef MODULE_PERIPH_MCG_LITE
 
typedef enum kinetis_mcg_mode {
    KINETIS_MCG_MODE_LIRC8M = 0, 
    KINETIS_MCG_MODE_HIRC   = 1, 
    KINETIS_MCG_MODE_EXT    = 2, 
    KINETIS_MCG_MODE_LIRC2M = 3, 
    KINETIS_MCG_MODE_NUMOF,    
} kinetis_mcg_mode_t;
#endif /* MODULE_PERIPH_MCG_LITE */
 
#ifdef MODULE_PERIPH_MCG
 
typedef enum kinetis_mcg_mode {
    KINETIS_MCG_MODE_FEI  = 0, 
    KINETIS_MCG_MODE_FEE  = 1, 
    KINETIS_MCG_MODE_FBI  = 2, 
    KINETIS_MCG_MODE_FBE  = 3, 
    KINETIS_MCG_MODE_BLPI = 4, 
    KINETIS_MCG_MODE_BLPE = 5, 
#if KINETIS_HAVE_PLL
    KINETIS_MCG_MODE_PBE  = 6, 
    KINETIS_MCG_MODE_PEE  = 7, 
#endif
    KINETIS_MCG_MODE_NUMOF,    
} kinetis_mcg_mode_t;
 
typedef enum {
    KINETIS_MCG_FLL_FACTOR_640  = (MCG_C4_DRST_DRS(0)),
    KINETIS_MCG_FLL_FACTOR_732  = (MCG_C4_DRST_DRS(0) | MCG_C4_DMX32_MASK),
    KINETIS_MCG_FLL_FACTOR_1280 = (MCG_C4_DRST_DRS(1)),
    KINETIS_MCG_FLL_FACTOR_1464 = (MCG_C4_DRST_DRS(1) | MCG_C4_DMX32_MASK),
    KINETIS_MCG_FLL_FACTOR_1920 = (MCG_C4_DRST_DRS(2)),
    KINETIS_MCG_FLL_FACTOR_2197 = (MCG_C4_DRST_DRS(2) | MCG_C4_DMX32_MASK),
    KINETIS_MCG_FLL_FACTOR_2560 = (MCG_C4_DRST_DRS(3)),
    KINETIS_MCG_FLL_FACTOR_2929 = (MCG_C4_DRST_DRS(3) | MCG_C4_DMX32_MASK),
} kinetis_mcg_fll_t;
 
#endif /* MODULE_PERIPH_MCG */
#if defined(MODULE_PERIPH_MCG) || defined(MODULE_PERIPH_MCG_LITE)
 
typedef enum {
    KINETIS_MCG_ERC_RANGE_LOW       = MCG_C2_RANGE0(0), 
    KINETIS_MCG_ERC_RANGE_HIGH      = MCG_C2_RANGE0(1), 
    KINETIS_MCG_ERC_RANGE_VERY_HIGH = MCG_C2_RANGE0(2), 
} kinetis_mcg_erc_range_t;
 
typedef enum {
    KINETIS_CLOCK_OSC0_EN           = (1 <<  0),
    KINETIS_CLOCK_RTCOSC_EN         = (1 <<  1),
    KINETIS_CLOCK_USE_FAST_IRC      = (1 <<  2),
    KINETIS_CLOCK_MCGIRCLK_EN       = (1 <<  3),
    KINETIS_CLOCK_MCGIRCLK_STOP_EN  = (1 <<  4),
    KINETIS_CLOCK_MCGPCLK_EN        = (1 <<  5),
} kinetis_clock_flags_t;
 
typedef struct {
    uint32_t clkdiv1;
    uint32_t rtc_clc;
    uint32_t osc32ksel;
    unsigned int clock_flags;
    kinetis_mcg_mode_t default_mode;
    kinetis_mcg_erc_range_t erc_range;
    uint8_t osc_clc;
#ifdef MODULE_PERIPH_MCG
 
    uint8_t oscsel;
#endif /* MODULE_PERIPH_MCG */
 
    uint8_t fcrdiv;
#ifdef MODULE_PERIPH_MCG_LITE
 
    uint8_t lirc_div2;
#else
 
    uint8_t fll_frdiv;
    kinetis_mcg_fll_t fll_factor_fei;
    kinetis_mcg_fll_t fll_factor_fee;
#if KINETIS_HAVE_PLL
 
    uint8_t pll_prdiv;
    uint8_t pll_vdiv;
#endif /* KINETIS_HAVE_PLL */
#endif /* MODULE_PERIPH_MCG */
} clock_config_t;
#endif /* MODULE_PERIPH_MCG || MODULE_PERIPH_MCG_LITE */
 
void gpio_init_port(gpio_t pin, uint32_t pcr);
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */