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cc26xx_cc13xx_gpt.h
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CC26XX_CC13XX_GPT_H
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#define CC26XX_CC13XX_GPT_H
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#include "
cc26xx_cc13xx.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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reg32_t
CFG
;
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reg32_t
TAMR
;
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reg32_t
TBMR
;
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reg32_t
CTL
;
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reg32_t
SYNC
;
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reg32_t
__reserved1
;
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reg32_t
IMR
;
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reg32_t
RIS
;
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reg32_t
MIS
;
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reg32_t
ICLR
;
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reg32_t
TAILR
;
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reg32_t
TBILR
;
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reg32_t
TAMATCHR
;
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reg32_t
TBMATCHR
;
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reg32_t
TAPR
;
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reg32_t
TBPR
;
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reg32_t
TAPMR
;
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reg32_t
TBPMR
;
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reg32_t
TAR
;
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reg32_t
TBR
;
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reg32_t
TAV
;
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reg32_t
TBV
;
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reg32_t
RTCPD
;
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reg32_t
TAPS
;
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reg32_t
TBPS
;
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reg32_t
TAPV
;
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reg32_t
TBPV
;
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reg32_t
DMAEV
;
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reg32_t __reserved2[976];
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reg32_t
VERSION
;
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reg32_t
ANDCCP
;
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}
gpt_reg_t
;
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#define GPT0_BASE (0x40010000)
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#define GPT1_BASE (0x40011000)
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#define GPT2_BASE (0x40012000)
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#define GPT3_BASE (0x40013000)
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#define GPT0 ((gpt_reg_t *) (GPT0_BASE))
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#define GPT1 ((gpt_reg_t *) (GPT1_BASE))
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#define GPT2 ((gpt_reg_t *) (GPT2_BASE))
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#define GPT3 ((gpt_reg_t *) (GPT3_BASE))
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#define GPT_CFG_32T 0
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#define GPT_CFG_32RTC 1
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#define GPT_CFG_16T 4
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#define GPT_TXMR_TXMR_ONE_SHOT 0x00000001
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#define GPT_TXMR_TXMR_PERIODIC 0x00000002
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#define GPT_TXMR_TXMR_CAPTURE 0x00000003
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#define GPT_TXMR_TXCM_EDGECNT 0x00000000
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#define GPT_TXMR_TXCM_EDGETIME 0x00000004
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#define GPT_TXMR_TXAMS_CAPTCOMP 0x00000000
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#define GPT_TXMR_TXAMS_PWM 0x00000008
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#define GPT_TXMR_TXCDIR_DOWN 0x00000000
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#define GPT_TXMR_TXCDIR_UP 0x00000010
/* starts from 0 */
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#define GPT_TXMR_TXMIE 0x00000020
/* match interrupt */
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#define GPT_TXMR_TXWOT 0x00000040
/* wait on trigger from daisy */
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#define GPT_TXMR_TXSNAPS 0x00000080
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#define GPT_TXMR_TXILD_CLOCK 0x00000000
/* interrupt loac: update TXPR or TXR */
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#define GPT_TXMR_TXILD_TIMEOUT 0x00000100
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#define GPT_TXMR_TXPWMIE 0x00000200
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#define GPT_TXMR_TXMRSU 0x00000400
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#define GPT_TXMR_TXPLO 0x00000800
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#define GPT_TXMR_TXCIN 0x00001000
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#define GPT_TXMR_TCACT_DIS 0x00000000
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#define GPT_TXMR_TCACT_TGL_TO 0x00002000
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#define GPT_TXMR_TCACT_CLR_TO 0x00004000
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#define GPT_TXMR_TCACT_SET_TO 0x00006000
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#define GPT_TXMR_TCACT_SET_NOW_TGL_TO 0x00008000
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#define GPT_TXMR_TCACT_CLR_NOW_TGL_TO 0x0000a000
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#define GPT_TXMR_TCACT_SET_NOW_CLR_TO 0x0000c000
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#define GPT_TXMR_TCACT_CLR_NOW_SET_TO 0x0000e000
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#define GPT_CTL_TAEN 0x00000001
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#define GPT_CTL_TASTALL 0x00000002
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#define GPT_CTL_TAEVENT_POS 0x00000000
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#define GPT_CTL_TAEVENT_NEG 0x00000004
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#define GPT_CTL_TAEVENT_BOTH 0x0000000c
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#define GPT_CTL_RTCEN 0x00000010
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#define GPT_CTL_TAPWML_INV 0x00000040
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#define GPT_CTL_TBEN 0x00000100
/* still need capture CFG */
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#define GPT_CTL_TBSTALL 0x00000200
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#define GPT_CTL_TBEVENT_POS 0x00000000
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#define GPT_CTL_TBEVENT_NEG 0x00000400
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#define GPT_CTL_TBEVENT_BOTH 0x00000c00
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#define GPT_CTL_TBPWML_INV 0x00004000
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#define GPT_SYNC_SYNC1_A 0x00000001
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#define GPT_SYNC_SYNC1_B 0x00000002
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#define GPT_SYNC_SYNC2_A 0x00000004
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#define GPT_SYNC_SYNC2_B 0x00000008
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#define GPT_SYNC_SYNC3_A 0x00000010
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#define GPT_SYNC_SYNC3_B 0x00000020
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#define GPT_SYNC_SYNC4_A 0x00000040
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#define GPT_SYNC_SYNC4_B 0x00000080
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#define GPT_IMR_TATOIM 0x00000001
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#define GPT_IMR_CAMIM 0x00000002
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#define GPT_IMR_CAEIM 0x00000004
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#define GPT_IMR_RTCIM 0x00000008
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#define GPT_IMR_TAMIM 0x00000010
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#define GPT_IMR_DMAAIM 0x00000020
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#define GPT_IMR_TBTOIM 0x00000100
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#define GPT_IMR_CBMIM 0x00000200
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#define GPT_IMR_CBEIM 0x00000400
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#define GPT_IMR_TBMIM 0x00000800
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#define GPT_IMR_DMABIM 0x00002000
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#define GPT_IMR_WUMIS 0x00010000
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#define GPT_RIS_TATORIS 0x00000001
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#define GPT_RIS_CAMRIS 0x00000002
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#define GPT_RIS_CAERIS 0x00000004
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#define GPT_RIS_RTCRIS 0x00000008
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#define GPT_RIS_TAMRIS 0x00000010
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#define GPT_RIS_TBTORIS 0x00000100
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#define GPT_RIS_CBMRIS 0x00000200
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#define GPT_RIS_CBERIS 0x00000400
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#define GPT_RIS_TBMRIS 0x00000800
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#define GPT_RIS_DMARIS 0x00002000
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#define GPT_RIS_WURIS 0x00010000
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#define GPT_MIS_TATOMIS 0x00000001
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#define GPT_MIS_CAMMIS 0x00000002
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#define GPT_MIS_CAEMIS 0x00000004
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#define GPT_MIS_RTCMIS 0x00000008
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#define GPT_MIS_TAMMIS 0x00000010
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#define GPT_MIS_TBTOMIS 0x00000100
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#define GPT_MIS_CBMMIS 0x00000200
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#define GPT_MIS_CBEMIS 0x00000400
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#define GPT_MIS_TBMMIS 0x00000800
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#define GPT_MIS_DMAMIS 0x00002000
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#define GPT_MIS_WUMIS 0x00010000
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#define GPT_ICLR_TATOCINT 0x00000001
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#define GPT_ICLR_CAMCINT 0x00000002
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#define GPT_ICLR_CAECINT 0x00000004
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#define GPT_ICLR_RTCCINT 0x00000008
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#define GPT_ICLR_TAMCINT 0x00000010
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#define GPT_ICLR_TBTOCINT 0x00000100
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#define GPT_ICLR_CBMCINT 0x00000200
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#define GPT_ICLR_CBECINT 0x00000400
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#define GPT_ICLR_TBMCINT 0x00000800
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#define GPT_ICLR_DMACINT 0x00002000
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#define GPT_ICLR_WUCINT 0x00010000
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#define GPT_DMAEV_TATODMAEN 0x00000001
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#define GPT_DMAEV_CAMDMAEN 0x00000002
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#define GPT_DMAEV_CAEDMAEN 0x00000004
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#define GPT_DMAEV_RTCDMAEN 0x00000008
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#define GPT_DMAEV_TAMDMAEN 0x00000010
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#define GPT_DMAEV_TBTODMAEN 0x00000100
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#define GPT_DMAEV_CBMDMAEN 0x00000200
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#define GPT_DMAEV_CBEDMAEN 0x00000400
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#define GPT_DMAEV_TBMDMAEN 0x00000800
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#define GPT_NUMOF 4
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#define NUM_CHANNELS_PER_GPT 1
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#ifdef __cplusplus
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}
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#endif
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#endif
/* CC26XX_CC13XX_GPT_H */
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gpt_reg_t::RTCPD
reg32_t RTCPD
config
Definition:
cc26xx_cc13xx_gpt.h:54
gpt_reg_t::TAR
reg32_t TAR
timer A register
Definition:
cc26xx_cc13xx_gpt.h:50
gpt_reg_t::IMR
reg32_t IMR
interrupt mask register
Definition:
cc26xx_cc13xx_gpt.h:38
gpt_reg_t::TBPR
reg32_t TBPR
timer B pre-scale
Definition:
cc26xx_cc13xx_gpt.h:47
gpt_reg_t::MIS
reg32_t MIS
masked interrupt status
Definition:
cc26xx_cc13xx_gpt.h:40
gpt_reg_t::TBV
reg32_t TBV
timer B value
Definition:
cc26xx_cc13xx_gpt.h:53
gpt_reg_t::CFG
reg32_t CFG
config
Definition:
cc26xx_cc13xx_gpt.h:32
gpt_reg_t::TBMATCHR
reg32_t TBMATCHR
timer B match register
Definition:
cc26xx_cc13xx_gpt.h:45
gpt_reg_t::TAMATCHR
reg32_t TAMATCHR
timer A match register
Definition:
cc26xx_cc13xx_gpt.h:44
gpt_reg_t::TBILR
reg32_t TBILR
timer B interval load register
Definition:
cc26xx_cc13xx_gpt.h:43
gpt_reg_t::TAPV
reg32_t TAPV
config
Definition:
cc26xx_cc13xx_gpt.h:57
gpt_reg_t::ICLR
reg32_t ICLR
interrupt clear
Definition:
cc26xx_cc13xx_gpt.h:41
gpt_reg_t::DMAEV
reg32_t DMAEV
config
Definition:
cc26xx_cc13xx_gpt.h:59
gpt_reg_t::SYNC
reg32_t SYNC
sync timers
Definition:
cc26xx_cc13xx_gpt.h:36
gpt_reg_t::TBR
reg32_t TBR
timer B register
Definition:
cc26xx_cc13xx_gpt.h:51
gpt_reg_t::TAILR
reg32_t TAILR
timer A interval load register
Definition:
cc26xx_cc13xx_gpt.h:42
gpt_reg_t::TAPS
reg32_t TAPS
config
Definition:
cc26xx_cc13xx_gpt.h:55
gpt_reg_t::TBMR
reg32_t TBMR
timer B mode
Definition:
cc26xx_cc13xx_gpt.h:34
gpt_reg_t::VERSION
reg32_t VERSION
config
Definition:
cc26xx_cc13xx_gpt.h:61
gpt_reg_t::TBPMR
reg32_t TBPMR
timer B pre-scale match register
Definition:
cc26xx_cc13xx_gpt.h:49
gpt_reg_t::TAMR
reg32_t TAMR
timer A mode
Definition:
cc26xx_cc13xx_gpt.h:33
gpt_reg_t::TAPMR
reg32_t TAPMR
timer A pre-scale match register
Definition:
cc26xx_cc13xx_gpt.h:48
cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
gpt_reg_t::CTL
reg32_t CTL
control
Definition:
cc26xx_cc13xx_gpt.h:35
gpt_reg_t::TAPR
reg32_t TAPR
timer A pre-scale
Definition:
cc26xx_cc13xx_gpt.h:46
gpt_reg_t::ANDCCP
reg32_t ANDCCP
config
Definition:
cc26xx_cc13xx_gpt.h:62
gpt_reg_t::TAV
reg32_t TAV
timer A value
Definition:
cc26xx_cc13xx_gpt.h:52
gpt_reg_t::RIS
reg32_t RIS
raw interrupt status
Definition:
cc26xx_cc13xx_gpt.h:39
gpt_reg_t::TBPV
reg32_t TBPV
config
Definition:
cc26xx_cc13xx_gpt.h:58
gpt_reg_t::__reserved1
reg32_t __reserved1
unused
Definition:
cc26xx_cc13xx_gpt.h:37
gpt_reg_t::TBPS
reg32_t TBPS
config
Definition:
cc26xx_cc13xx_gpt.h:56
gpt_reg_t
GPT registers.
Definition:
cc26xx_cc13xx_gpt.h:31
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