cfg_clock_default_208.h
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1 /*
2  * Copyright (C) 2020 Savoir-faire Linux
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef CLK_MP1_CFG_CLOCK_DEFAULT_208_H
20 #define CLK_MP1_CFG_CLOCK_DEFAULT_208_H
21 
22 #include "mp1/cfg_clock_common.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* The following parameters configure a 208MHz system clock with HSE (24MHz)
33  * or HSI (16MHz) as PLL input clock */
34 #ifndef CONFIG_CLOCK_PLL_M
35 #define CONFIG_CLOCK_PLL_M (2)
36 #endif
37 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(24))
38 #ifndef CONFIG_CLOCK_PLL_N
39 #define CONFIG_CLOCK_PLL_N (52)
40 #endif
41 #else /* HSI */
42 #ifndef CONFIG_CLOCK_PLL_N
43 #define CONFIG_CLOCK_PLL_N (78)
44 #endif
45 #endif
46 #ifndef CONFIG_CLOCK_PLL_P
47 #define CONFIG_CLOCK_PLL_P (3)
48 #endif
49 #ifndef CONFIG_CLOCK_PLL_Q
50 #define CONFIG_CLOCK_PLL_Q (13)
51 #endif
52 #ifndef CONFIG_CLOCK_PLL_R
53 #define CONFIG_CLOCK_PLL_R (3)
54 #endif
55 
60 #ifndef CONFIG_CLOCK_MCU_DIV
61 #define CONFIG_CLOCK_MCU_DIV (1) /* max 208MHz */
62 #endif
63 #ifndef CONFIG_CLOCK_APB1_DIV
64 #define CONFIG_CLOCK_APB1_DIV (2) /* max 104MHz */
65 #endif
66 #ifndef CONFIG_CLOCK_APB2_DIV
67 #define CONFIG_CLOCK_APB2_DIV (2) /* max 104MHz */
68 #endif
69 #ifndef CONFIG_CLOCK_APB3_DIV
70 #define CONFIG_CLOCK_APB3_DIV (2) /* max 104MHz */
71 #endif
72 
74 #ifdef __cplusplus
75 }
76 #endif
77 
78 #include "mp1/cfg_clock_values.h"
79 
80 #if CLOCK_CORECLOCK > MHZ(208)
81 #error "SYSCLK cannot exceed 208MHz"
82 #endif
83 
84 #endif /* CLK_MP1_CFG_CLOCK_DEFAULT_208_H */
85 
cfg_clock_common.h
Base STM32MP1 clock configuration.
cfg_clock_values.h
STM32MP1 clock values definitions.