cfg_clock_default.h
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1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef CLK_F0_CFG_CLOCK_DEFAULT_H
22 #define CLK_F0_CFG_CLOCK_DEFAULT_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* Select the desired system clock source between PLL, HSE or HSI */
33 #ifndef CONFIG_USE_CLOCK_PLL
34 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
35 #define CONFIG_USE_CLOCK_PLL 0
36 #else
37 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
38 #endif
39 #endif /* CONFIG_USE_CLOCK_PLL */
40 
41 #ifndef CONFIG_USE_CLOCK_HSE
42 #define CONFIG_USE_CLOCK_HSE 0
43 #endif /* CONFIG_USE_CLOCK_HSE */
44 
45 #ifndef CONFIG_USE_CLOCK_HSI
46 #define CONFIG_USE_CLOCK_HSI 0
47 #endif /* CONFIG_USE_CLOCK_HSI */
48 
49 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
50  (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
51 #error "Cannot use PLL as clock source with other clock configurations"
52 #endif
53 
54 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
55  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
56 #error "Cannot use HSE as clock source with other clock configurations"
57 #endif
58 
59 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
60  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
61 #error "Cannot use HSI as clock source with other clock configurations"
62 #endif
63 
64 #ifndef CONFIG_BOARD_HAS_HSE
65 #define CONFIG_BOARD_HAS_HSE 0
66 #endif
67 
68 #ifndef CLOCK_HSE
69 #define CLOCK_HSE MHZ(8)
70 #endif
71 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
72 #error "HSE clock frequency must be between 4MHz and 32MHz"
73 #endif
74 
75 #ifndef CONFIG_BOARD_HAS_LSE
76 #define CONFIG_BOARD_HAS_LSE 0
77 #endif
78 
79 #define CLOCK_HSI MHZ(8)
80 
81 /* The following parameters configure a 48MHz system clock with HSI (or default HSE) as input clock
82 On stm32f031x6 and stm32f042x6 lines, there's no HSE and PREDIV is hard-wired to 2,
83 so to reach 48MHz set PLL_PREDIV to 2 and PLL_MUL to 12 so core clock = (HSI8 / 2) * 12 = 48MHz */
84 #ifndef CONFIG_CLOCK_PLL_PREDIV
85 #if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
86 #define CONFIG_CLOCK_PLL_PREDIV (2)
87 #else
88 #define CONFIG_CLOCK_PLL_PREDIV (1)
89 #endif
90 #endif
91 #ifndef CONFIG_CLOCK_PLL_MUL
92 #if defined(CPU_LINE_STM32F031x6) || defined(CPU_LINE_STM32F042x6)
93 #define CONFIG_CLOCK_PLL_MUL (12)
94 #else
95 #define CONFIG_CLOCK_PLL_MUL (6)
96 #endif
97 #endif
98 
99 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
100 #define CLOCK_CORECLOCK (CLOCK_HSI)
101 
102 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
103 #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
104 #error "The board doesn't provide an HSE oscillator"
105 #endif
106 #define CLOCK_CORECLOCK (CLOCK_HSE)
107 
108 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
109 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
110 #define CLOCK_PLL_SRC (CLOCK_HSE)
111 #else /* CLOCK_HSI */
112 #define CLOCK_PLL_SRC (CLOCK_HSI)
113 #endif
114 /* PLL configuration: make sure your values are legit!
115  *
116  * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
117  * with:
118  * PLL_IN: input clock is HSE if available or HSI otherwise
119  * PLL_PREDIV : pre-divider, allowed range: [1:16]
120  * PLL_MUL: multiplier, allowed range: [2:16]
121  * CORECLOCK -> 48MHz MAX!
122  */
123 #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
124 #if CLOCK_CORECLOCK > MHZ(48)
125 #error "SYSCLK cannot exceed 48MHz"
126 #endif
127 #endif /* CONFIG_USE_CLOCK_PLL */
128 
129 #define CLOCK_AHB CLOCK_CORECLOCK /* max: 48MHz */
130 
131 #ifndef CONFIG_CLOCK_APB1_DIV
132 #define CONFIG_CLOCK_APB1_DIV (1)
133 #endif
134 #define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 48MHz */
135 /* APB2 and APB1 are the same bus but configuration registers still follows the
136  * split between APB1 and APB2. Since it's the same bus, APB2 clock is equal to APB1 clock.
137  */
138 #define CLOCK_APB2 (CLOCK_APB1)
139 
141 #ifdef __cplusplus
142 }
143 #endif
144 
145 #endif /* CLK_F0_CFG_CLOCK_DEFAULT_H */
146