cfg_clock_default.h
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1 /*
2  * Copyright (C) 2015 TriaGnoSys GmbH
3  * 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
4  * 2020 Inria
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
26 #ifndef CLK_F1F3_CFG_CLOCK_DEFAULT_H
27 #define CLK_F1F3_CFG_CLOCK_DEFAULT_H
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
37 /* Select the desired system clock source between PLL, HSE or HSI */
38 #ifndef CONFIG_USE_CLOCK_PLL
39 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
40 #define CONFIG_USE_CLOCK_PLL 0
41 #else
42 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
43 #endif
44 #endif /* CONFIG_USE_CLOCK_PLL */
45 
46 #ifndef CONFIG_USE_CLOCK_HSE
47 #define CONFIG_USE_CLOCK_HSE 0
48 #endif /* CONFIG_USE_CLOCK_HSE */
49 
50 #ifndef CONFIG_USE_CLOCK_HSI
51 #define CONFIG_USE_CLOCK_HSI 0
52 #endif /* CONFIG_USE_CLOCK_HSI */
53 
54 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
55  (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
56 #error "Cannot use PLL as clock source with other clock configurations"
57 #endif
58 
59 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
60  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
61 #error "Cannot use HSE as clock source with other clock configurations"
62 #endif
63 
64 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
65  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
66 #error "Cannot use HSI as clock source with other clock configurations"
67 #endif
68 
69 #ifndef CONFIG_BOARD_HAS_HSE
70 #define CONFIG_BOARD_HAS_HSE 0
71 #endif
72 
73 #ifndef CLOCK_HSE
74 #define CLOCK_HSE MHZ(8)
75 #endif
76 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(32))
77 #error "HSE clock frequency must be between 4MHz and 32MHz"
78 #endif
79 
80 #ifndef CONFIG_BOARD_HAS_LSE
81 #define CONFIG_BOARD_HAS_LSE 0
82 #endif
83 
84 #define CLOCK_HSI MHZ(8)
85 
86 /* The following parameters configure a 72MHz system clock with HSE (8MHz or
87  16MHz) and HSI (8MHz) as input clock */
88 #ifndef CONFIG_CLOCK_PLL_PREDIV
89 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(16))
90 #define CONFIG_CLOCK_PLL_PREDIV (2)
91 #else
92 #define CONFIG_CLOCK_PLL_PREDIV (1)
93 #endif
94 #endif
95 #ifndef CONFIG_CLOCK_PLL_MUL
96 #define CONFIG_CLOCK_PLL_MUL (9)
97 #endif
98 
99 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
100 #define CLOCK_CORECLOCK (CLOCK_HSI)
101 
102 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
103 #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
104 #error "The board doesn't provide an HSE oscillator"
105 #endif
106 #define CLOCK_CORECLOCK (CLOCK_HSE)
107 
108 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
109 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
110 #define CLOCK_PLL_SRC (CLOCK_HSE)
111 #else /* CLOCK_HSI */
112 #define CLOCK_PLL_SRC (CLOCK_HSI)
113 #endif
114 /* PLL configuration: make sure your values are legit!
115  *
116  * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
117  * with:
118  * PLL_IN: input clock is HSE if available or HSI otherwise
119  * PLL_PREDIV : pre-divider, allowed range: [1:16]
120  * PLL_MUL: multiplier, allowed range: [2:16]
121  * CORECLOCK -> 72MHz MAX!
122  */
123 #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_PREDIV) * CONFIG_CLOCK_PLL_MUL)
124 #if CLOCK_CORECLOCK > MHZ(72)
125 #error "SYSCLK cannot exceed 72MHz"
126 #endif
127 #endif /* CONFIG_USE_CLOCK_PLL */
128 
129 #define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 72MHz */
130 
131 #ifndef CONFIG_CLOCK_APB1_DIV
132 #define CONFIG_CLOCK_APB1_DIV (2)
133 #endif
134 #define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 36MHz */
135 #ifndef CONFIG_CLOCK_APB2_DIV
136 #define CONFIG_CLOCK_APB2_DIV (1)
137 #endif
138 #define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK2, max: 72MHz */
139 
141 #ifdef __cplusplus
142 }
143 #endif
144 
145 #endif /* CLK_F1F3_CFG_CLOCK_DEFAULT_H */
146