Configure STM32G0 clock. More...

Detailed Description

Configure STM32G0 clock.

CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz. Default configuration use PLL clock as system clock. PLL input clock is HSI by default.

Author: Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file cfg_clock_default.h.

Clock settings
#define	CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */

#define	CONFIG_USE_CLOCK_HSE 0

#define	CONFIG_USE_CLOCK_HSI 0

#define	CONFIG_BOARD_HAS_HSE 0

#define	CLOCK_HSE MHZ(24)

#define	CONFIG_BOARD_HAS_LSE 0

#define	CLOCK_HSI MHZ(16)

#define	CONFIG_CLOCK_HSISYS_DIV (1)

#define	CLOCK_PLL_SRC (CLOCK_HSI)

#define	CONFIG_CLOCK_PLL_M (1)

#define	CONFIG_CLOCK_PLL_N (20)

#define	CONFIG_CLOCK_PLL_R (5)

#define	CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz */

#define	CONFIG_CLOCK_APB1_DIV (1)

#define	CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz */

Clock settings