cfg_clock_default.h
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1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
23 #ifndef CLK_G0_CFG_CLOCK_DEFAULT_H
24 #define CLK_G0_CFG_CLOCK_DEFAULT_H
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
35 /* Select the desired system clock source between PLL, HSE or HSI */
36 #ifndef CONFIG_USE_CLOCK_PLL
37 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
38 #define CONFIG_USE_CLOCK_PLL 0
39 #else
40 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
41 #endif
42 #endif /* CONFIG_USE_CLOCK_PLL */
43 
44 #ifndef CONFIG_USE_CLOCK_HSE
45 #define CONFIG_USE_CLOCK_HSE 0
46 #endif /* CONFIG_USE_CLOCK_HSE */
47 
48 #ifndef CONFIG_USE_CLOCK_HSI
49 #define CONFIG_USE_CLOCK_HSI 0
50 #endif /* CONFIG_USE_CLOCK_HSI */
51 
52 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
53  (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
54 #error "Cannot use PLL as clock source with other clock configurations"
55 #endif
56 
57 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
58  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
59 #error "Cannot use HSE as clock source with other clock configurations"
60 #endif
61 
62 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
63  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
64 #error "Cannot use HSI as clock source with other clock configurations"
65 #endif
66 
67 #ifndef CONFIG_BOARD_HAS_HSE
68 #define CONFIG_BOARD_HAS_HSE 0
69 #endif
70 
71 #ifndef CLOCK_HSE
72 #define CLOCK_HSE MHZ(24)
73 #endif
74 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
75 #error "HSE clock frequency must be between 4MHz and 48MHz"
76 #endif
77 
78 #ifndef CONFIG_BOARD_HAS_LSE
79 #define CONFIG_BOARD_HAS_LSE 0
80 #endif
81 
82 #define CLOCK_HSI MHZ(16)
83 
84 #ifndef CONFIG_CLOCK_HSISYS_DIV
85 #define CONFIG_CLOCK_HSISYS_DIV (1)
86 #endif
87 
88 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
89 #define CLOCK_PLL_SRC (CLOCK_HSE)
90 #else /* CLOCK_HSI */
91 #define CLOCK_PLL_SRC (CLOCK_HSI)
92 #endif
93 
94 /* The following parameters configure a 64MHz system clock with HSI as input clock */
95 #ifndef CONFIG_CLOCK_PLL_M
96 #define CONFIG_CLOCK_PLL_M (1)
97 #endif
98 #ifndef CONFIG_CLOCK_PLL_N
99 #define CONFIG_CLOCK_PLL_N (20)
100 #endif
101 #ifndef CONFIG_CLOCK_PLL_R
102 #define CONFIG_CLOCK_PLL_R (5)
103 #endif
104 
105 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
106 #define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
107 
108 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
109 #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
110 #error "The board doesn't provide an HSE oscillator"
111 #endif
112 #define CLOCK_CORECLOCK (CLOCK_HSE)
113 
114 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
115 #define CLOCK_CORECLOCK \
116  ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
117 #if CLOCK_CORECLOCK > MHZ(64)
118 #error "SYSCLK cannot exceed 64MHz"
119 #endif
120 #endif /* CONFIG_USE_CLOCK_PLL */
121 
122 #define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz */
123 
124 #ifndef CONFIG_CLOCK_APB1_DIV
125 #define CONFIG_CLOCK_APB1_DIV (1)
126 #endif
127 #define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz */
128 
130 #ifdef __cplusplus
131 }
132 #endif
133 
134 #endif /* CLK_G0_CFG_CLOCK_DEFAULT_H */
135