cfg_clock_default.h
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1 /*
2  * Copyright (C) 2018-2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CLK_L0L1_CFG_CLOCK_DEFAULT_H
20 #define CLK_L0L1_CFG_CLOCK_DEFAULT_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* Select the desired system clock source between PLL, HSE or HSI */
33 #ifndef CONFIG_USE_CLOCK_PLL
34 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
35  IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
36 #define CONFIG_USE_CLOCK_PLL 0
37 #else
38 #define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
39 #endif
40 #endif /* CONFIG_USE_CLOCK_PLL */
41 
42 #ifndef CONFIG_USE_CLOCK_MSI
43 #define CONFIG_USE_CLOCK_MSI 0
44 #endif /* CONFIG_USE_CLOCK_MSI */
45 
46 #ifndef CONFIG_USE_CLOCK_HSE
47 #define CONFIG_USE_CLOCK_HSE 0
48 #endif /* CONFIG_USE_CLOCK_HSE */
49 
50 #ifndef CONFIG_USE_CLOCK_HSI
51 #define CONFIG_USE_CLOCK_HSI 0
52 #endif /* CONFIG_USE_CLOCK_HSI */
53 
54 #if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
55  (IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
56  IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
57 #error "Cannot use PLL as clock source with other clock configurations"
58 #endif
59 
60 #if IS_ACTIVE(CONFIG_USE_CLOCK_MSI) && \
61  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
62  IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
63 #error "Cannot use MSI as clock source with other clock configurations"
64 #endif
65 
66 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
67  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
68  IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
69 #error "Cannot use HSE as clock source with other clock configurations"
70 #endif
71 
72 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
73  (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_MSI) || \
74  IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
75 #error "Cannot use HSI as clock source with other clock configurations"
76 #endif
77 
78 #ifndef CONFIG_BOARD_HAS_HSE
79 #define CONFIG_BOARD_HAS_HSE 0
80 #endif
81 
82 #ifndef CLOCK_HSE
83 #define CLOCK_HSE MHZ(24)
84 #endif
85 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
86 #error "HSE clock frequency must be between 1MHz and 24MHz"
87 #endif
88 
89 #ifndef CONFIG_BOARD_HAS_LSE
90 #define CONFIG_BOARD_HAS_LSE 0
91 #endif
92 
93 #define CLOCK_HSI MHZ(16)
94 
95 #ifndef CONFIG_CLOCK_MSI
96 #define CONFIG_CLOCK_MSI KHZ(4194)
97 #endif
98 
99 /* The following parameters configure a 32MHz system clock with HSI as input clock */
100 #ifndef CONFIG_CLOCK_PLL_DIV
101 #define CONFIG_CLOCK_PLL_DIV (2)
102 #endif
103 #ifndef CONFIG_CLOCK_PLL_MUL
104 #define CONFIG_CLOCK_PLL_MUL (4)
105 #endif
106 
107 #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
108 #define CLOCK_CORECLOCK (CLOCK_HSI)
109 
110 #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
111 #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
112 #error "The board doesn't provide an HSE oscillator"
113 #endif
114 #define CLOCK_CORECLOCK (CLOCK_HSE)
115 
116 #elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
117 #define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
118 
119 #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
120 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
121 #if CLOCK_HSE < MHZ(2)
122 #error "HSE must be greater than 2MHz when used as PLL input clock"
123 #endif
124 #define CLOCK_PLL_SRC (CLOCK_HSE)
125 #else /* CLOCK_HSI */
126 #define CLOCK_PLL_SRC (CLOCK_HSI)
127 #endif /* CONFIG_BOARD_HAS_HSE */
128 /* PLL configuration: make sure your values are legit!
129  *
130  * compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
131  * with:
132  * PLL_IN: input clock is HSE if available or HSI otherwise
133  * PLL_DIV : divider, allowed values: 2, 3, 4. Default is 2.
134  * PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48. Default is 4.
135  * CORECLOCK -> 32MHz MAX!
136  */
137 #define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
138 #if CLOCK_CORECLOCK > MHZ(32)
139 #error "SYSCLK cannot exceed 32MHz"
140 #endif
141 #endif /* CONFIG_USE_CLOCK_PLL */
142 
143 #define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */
144 
145 #ifndef CONFIG_CLOCK_APB1_DIV
146 #define CONFIG_CLOCK_APB1_DIV (1)
147 #endif
148 #define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */
149 #ifndef CONFIG_CLOCK_APB2_DIV
150 #define CONFIG_CLOCK_APB2_DIV (1)
151 #endif
152 #define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
153 
155 #ifdef __cplusplus
156 }
157 #endif
158 
159 #endif /* CLK_L0L1_CFG_CLOCK_DEFAULT_H */
160