clk_conf.h
1 /*
2  * Copyright (C) 2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
18 #ifndef CLK_CONF_H
19 #define CLK_CONF_H
20 
21 #include <stdbool.h>
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
31 enum fam {
32  STM32F0,
33  STM32F1,
34  STM32F2,
35  STM32F3,
36  STM32F4,
37  STM32F7,
38  STM32MP1,
39  FAM_MAX,
40 };
47 enum {
48  STM32F030,
49  STM32F070,
50  STM32F031,
51  STM32F051,
52  STM32F071,
53  STM32F091,
54  STM32F042,
55  STM32F072,
56  STM32F038,
57  STM32F048,
58  STM32F058,
59  STM32F078,
60  STM32F098,
61 
62  STM32F100,
63  STM32F101,
64  STM32F102,
65  STM32F103,
66 
67  STM32F205,
68  STM32F207,
69  STM32F215,
70  STM32F217,
71 
72  STM32F301,
73  STM32F302,
74  STM32F303,
75  STM32F334,
76  STM32F373,
77  STM32F318,
78  STM32F328,
79  STM32F358,
80  STM32F378,
81  STM32F398,
82 
83  STM32F401,
84  STM32F405,
85  STM32F407,
86  STM32F410,
87  STM32F411,
88  STM32F412,
89  STM32F413,
90  STM32F415,
91  STM32F417,
92  STM32F423,
93  STM32F427,
94  STM32F429,
95  STM32F437,
96  STM32F439,
97  STM32F446,
98  STM32F469,
99  STM32F479,
100 
101  STM32F722,
102  STM32F732,
103  STM32F746,
104  STM32F756,
105  STM32F767,
106  STM32F769,
107  STM32F777,
108  STM32F779,
109 
110  MODEL_F_MAX,
111 };
112 
113 enum {
114  STM32MP157,
115 
116  MODEL_MP_MAX,
117 };
118 
146 typedef struct {
147  unsigned min_vco_input;
148  unsigned max_vco_input;
149  unsigned min_vco_output;
150  unsigned max_vco_output;
152  unsigned min_n;
153  unsigned max_n;
154  unsigned inc_n;
156  unsigned min_m;
157  unsigned max_m;
158  unsigned inc_m;
160  unsigned min_p;
161  unsigned max_p;
162  unsigned inc_p;
164  unsigned min_q;
165  unsigned max_q;
166  unsigned inc_q;
167 } pll_cfg_t;
168 
172 typedef struct {
173  enum fam family;
175  unsigned max_coreclock;
176  unsigned max_apb1;
177  unsigned max_apb2;
178  unsigned max_apb3;
180  unsigned hsi;
182  pll_cfg_t pll;
184  bool has_pll_i2s;
185  bool has_pll_sai;
186  bool has_pll_i2s_m;
187  bool has_pll_sai_m;
188  bool has_pll_i2s_alt_input;
190  unsigned hsi_prediv;
192  int has_alt_48MHz;
193  bool need_48MHz;
194 } clk_cfg_t;
195 
200 #define ALT_48MHZ_NO 0
201 #define ALT_48MHZ_I2S 1
202 #define ALT_48MHZ_SAI 2
203 
204 #define ALT_48MHZ_Q 0
205 #define ALT_48MHZ_P 4
206 
208 #define STM32F(x) [STM32F##x] = x
209 #define STM32F0(x) [STM32F0##x] = x
210 
212 static const unsigned stm32_f_model[] = {
213  STM32F0(30),
214  STM32F0(70),
215  STM32F0(31),
216  STM32F0(51),
217  STM32F0(71),
218  STM32F0(91),
219  STM32F0(42),
220  STM32F0(72),
221  STM32F0(38),
222  STM32F0(48),
223  STM32F0(58),
224  STM32F0(78),
225  STM32F0(98),
226 
227  STM32F(100),
228  STM32F(101),
229  STM32F(102),
230  STM32F(103),
231 
232  STM32F(205),
233  STM32F(207),
234  STM32F(215),
235  STM32F(217),
236 
237  STM32F(301),
238  STM32F(302),
239  STM32F(303),
240  STM32F(334),
241  STM32F(373),
242  STM32F(318),
243  STM32F(328),
244  STM32F(358),
245  STM32F(378),
246  STM32F(398),
247 
248  STM32F(401),
249  STM32F(405),
250  STM32F(407),
251  STM32F(410),
252  STM32F(411),
253  STM32F(412),
254  STM32F(413),
255  STM32F(415),
256  STM32F(417),
257  STM32F(423),
258  STM32F(427),
259  STM32F(429),
260  STM32F(437),
261  STM32F(439),
262  STM32F(446),
263  STM32F(469),
264  STM32F(479),
265 
266  STM32F(722),
267  STM32F(732),
268  STM32F(746),
269  STM32F(756),
270  STM32F(767),
271  STM32F(769),
272  STM32F(777),
273  STM32F(779),
274 };
275 
276 #define STM32MP(x) [STM32MP##x] = x
277 
279 static const unsigned stm32_model_mp[] = {
280  STM32MP(157),
281 };
282 
284 #define stm32f2_4_192_pll_cfg { \
285  .min_vco_input = 1000000U, \
286  .max_vco_input = 2000000U, \
287  .min_vco_output = 192000000U, \
288  .max_vco_output = 432000000U, \
289  .min_n = 50, \
290  .max_n = 432, \
291  .inc_n = 1, \
292  .min_m = 2, \
293  .max_m = 63, \
294  .inc_m = 1, \
295  .min_p = 2, \
296  .max_p = 8, \
297  .inc_p = 2, \
298  .min_q = 2, \
299  .max_q = 15, \
300  .inc_q = 1, \
301 }
302 
304 #define stm32f4_7_pll_cfg { \
305  .min_vco_input = 1000000U, \
306  .max_vco_input = 2000000U, \
307  .min_vco_output = 192000000U, \
308  .max_vco_output = 432000000U, \
309  .min_n = 50, \
310  .max_n = 432, \
311  .inc_n = 1, \
312  .min_m = 2, \
313  .max_m = 63, \
314  .inc_m = 1, \
315  .min_p = 2, \
316  .max_p = 8, \
317  .inc_p = 2, \
318  .min_q = 2, \
319  .max_q = 15, \
320  .inc_q = 1, \
321 }
322 
324 #define stm32mp1_pll_cfg { \
325  .min_vco_input = 4000000U, \
326  .max_vco_input = 16000000U, \
327  .min_vco_output = 400000000U, \
328  .max_vco_output = 800000000U, \
329  .min_n = 25, \
330  .max_n = 100, \
331  .inc_n = 1, \
332  .min_m = 2, \
333  .max_m = 63, \
334  .inc_m = 1, \
335  .min_p = 2, \
336  .max_p = 127, \
337  .inc_p = 1, \
338  .min_q = 2, \
339  .max_q = 127, \
340  .inc_q = 1, \
341 }
342 
346 static const clk_cfg_t stm32_f_clk_cfg[] = {
347  [STM32F030 ... STM32F098] = {
348  .family = STM32F0,
349  .max_coreclock = 48000000U,
350  .max_apb1 = 48000000U,
351  .max_apb2 = 0,
352  .hsi = 8000000U,
353  .pll = {
354  .min_vco_input = 1000000U,
355  .max_vco_input = 24000000U,
356  .min_vco_output = 16000000U,
357  .max_vco_output = 48000000U,
358  .min_m = 1,
359  .max_m = 16,
360  .inc_m = 1,
361  .min_n = 2,
362  .max_n = 16,
363  .inc_n = 1,
364  .min_p = 1,
365  .max_p = 1,
366  .inc_p = 1,
367  },
368  .has_pll_i2s = false,
369  .has_pll_sai = false,
370  .has_pll_i2s_alt_input = false,
371  .has_alt_48MHz = 0,
372  .hsi_prediv = 2,
373  .need_48MHz = false,
374  },
375  [STM32F100] = {
376  .family = STM32F1,
377  .max_coreclock = 24000000U,
378  .max_apb1 = 24000000U,
379  .max_apb2 = 24000000U,
380  .hsi = 8000000U,
381  .pll = {
382  .min_vco_input = 1000000U,
383  .max_vco_input = 24000000U,
384  .min_vco_output = 16000000U,
385  .max_vco_output = 24000000U,
386  .min_m = 1,
387  .max_m = 16,
388  .inc_m = 1,
389  .min_n = 2,
390  .max_n = 16,
391  .inc_n = 1,
392  .min_p = 1,
393  .max_p = 1,
394  .inc_p = 1,
395  },
396  .has_pll_i2s = false,
397  .has_pll_sai = false,
398  .has_pll_i2s_alt_input = false,
399  .has_alt_48MHz = 0,
400  .hsi_prediv = 2,
401  .need_48MHz = false,
402  },
403  [STM32F101 ... STM32F103] = {
404  .family = STM32F1,
405  .max_coreclock = 72000000U,
406  .max_apb1 = 36000000U,
407  .max_apb2 = 72000000U,
408  .hsi = 8000000U,
409  .pll = {
410  .min_vco_input = 1000000U,
411  .max_vco_input = 25000000U,
412  .min_vco_output = 1000000U,
413  .max_vco_output = 72000000U,
414  .min_m = 1,
415  .max_m = 16,
416  .inc_m = 1,
417  .min_n = 2,
418  .max_n = 16,
419  .inc_n = 1,
420  .min_p = 1,
421  .max_p = 1,
422  .inc_p = 1,
423  },
424  .has_pll_i2s = false,
425  .has_pll_sai = false,
426  .has_pll_i2s_alt_input = false,
427  .has_alt_48MHz = 0,
428  .hsi_prediv = 2,
429  .need_48MHz = false,
430  },
431  [STM32F205 ... STM32F217] = {
432  .family = STM32F2,
433  .max_coreclock = 120000000U,
434  .max_apb1 = 30000000U,
435  .max_apb2 = 60000000U,
436  .hsi = 16000000U,
437  .pll = stm32f2_4_192_pll_cfg,
438  .has_pll_i2s = true,
439  .has_pll_sai = false,
440  .has_pll_i2s_alt_input = false,
441  .has_alt_48MHz = 0,
442  .need_48MHz = true,
443  },
444  [STM32F301 ... STM32F398] = {
445  .family = STM32F3,
446  .max_coreclock = 72000000U,
447  .max_apb1 = 36000000U,
448  .max_apb2 = 72000000U,
449  .hsi = 8000000U,
450  .pll = {
451  .min_vco_input = 1000000U,
452  .max_vco_input = 25000000U,
453  .min_vco_output = 1000000U,
454  .max_vco_output = 72000000U,
455  .min_m = 1,
456  .max_m = 16,
457  .inc_m = 1,
458  .min_n = 2,
459  .max_n = 16,
460  .inc_n = 1,
461  .min_p = 1,
462  .max_p = 1,
463  .inc_p = 1,
464  },
465  .has_pll_i2s = false,
466  .has_pll_sai = false,
467  .has_pll_i2s_alt_input = false,
468  .has_alt_48MHz = 0,
469  .hsi_prediv = 2,
470  .need_48MHz = false,
471  },
472  [STM32F401] = {
473  .family = STM32F4,
474  .max_coreclock = 84000000U,
475  .max_apb1 = 42000000U,
476  .max_apb2 = 84000000U,
477  .hsi = 16000000U,
478  .pll = stm32f2_4_192_pll_cfg,
479  .has_pll_i2s = true,
480  .has_pll_sai = false,
481  .has_pll_i2s_m = false,
482  .has_pll_i2s_alt_input = false,
483  .has_alt_48MHz = 0,
484  .need_48MHz = true,
485  },
486  [STM32F405 ... STM32F407] = {
487  .family = STM32F4,
488  .max_coreclock = 168000000U,
489  .max_apb1 = 42000000U,
490  .max_apb2 = 84000000U,
491  .hsi = 16000000U,
492  .pll = stm32f4_7_pll_cfg,
493  .has_pll_i2s = true,
494  .has_pll_sai = false,
495  .has_pll_i2s_m = false,
496  .has_pll_i2s_alt_input = false,
497  .has_alt_48MHz = 0,
498  .need_48MHz = true,
499  },
500  [STM32F410] = {
501  .family = STM32F4,
502  .max_coreclock = 100000000U,
503  .max_apb1 = 50000000U,
504  .max_apb2 = 100000000U,
505  .hsi = 16000000U,
506  .pll = stm32f4_7_pll_cfg,
507  .has_pll_i2s = false,
508  .has_pll_sai = false,
509  .has_pll_i2s_m = false,
510  .has_pll_i2s_alt_input = false,
511  .has_alt_48MHz = 0,
512  .need_48MHz = true,
513  },
514  [STM32F411] = {
515  .family = STM32F4,
516  .max_coreclock = 100000000U,
517  .max_apb1 = 50000000U,
518  .max_apb2 = 100000000U,
519  .hsi = 16000000U,
520  .pll = stm32f4_7_pll_cfg,
521  .has_pll_i2s = true,
522  .has_pll_sai = false,
523  .has_pll_i2s_m = true,
524  .has_pll_i2s_alt_input = false,
525  .has_alt_48MHz = 0,
526  .need_48MHz = true,
527  },
528  [STM32F412 ... STM32F413] = {
529  .family = STM32F4,
530  .max_coreclock = 100000000U,
531  .max_apb1 = 50000000U,
532  .max_apb2 = 100000000U,
533  .hsi = 16000000U,
534  .pll = stm32f4_7_pll_cfg,
535  .has_pll_i2s = true,
536  .has_pll_sai = true,
537  .has_pll_i2s_m = true,
538  .has_pll_sai_m = false,
539  .has_pll_i2s_alt_input = true,
540  .has_alt_48MHz = ALT_48MHZ_I2S,
541  .need_48MHz = true,
542  },
543  [STM32F415 ... STM32F417] = {
544  .family = STM32F4,
545  .max_coreclock = 168000000U,
546  .max_apb1 = 42000000U,
547  .max_apb2 = 84000000U,
548  .hsi = 16000000U,
549  .pll = stm32f4_7_pll_cfg,
550  .has_pll_i2s = true,
551  .has_pll_sai = false,
552  .has_pll_i2s_m = false,
553  .has_pll_i2s_alt_input = false,
554  .has_alt_48MHz = 0,
555  .need_48MHz = true,
556  },
557  [STM32F423] = {
558  .family = STM32F4,
559  .max_coreclock = 100000000U,
560  .max_apb1 = 50000000U,
561  .max_apb2 = 100000000U,
562  .hsi = 16000000U,
563  .pll = stm32f4_7_pll_cfg,
564  .has_pll_i2s = true,
565  .has_pll_sai = true,
566  .has_pll_i2s_m = true,
567  .has_pll_sai_m = false,
568  .has_pll_i2s_alt_input = true,
569  .has_alt_48MHz = ALT_48MHZ_I2S,
570  .need_48MHz = true,
571  },
572  [STM32F427 ... STM32F439] = {
573  .family = STM32F4,
574  .max_coreclock = 180000000U,
575  .max_apb1 = 45000000U,
576  .max_apb2 = 90000000U,
577  .hsi = 16000000U,
578  .pll = stm32f4_7_pll_cfg,
579  .has_pll_i2s = true,
580  .has_pll_sai = true,
581  .has_pll_i2s_m = false,
582  .has_pll_sai_m = false,
583  .has_pll_i2s_alt_input = false,
584  .has_alt_48MHz = 0,
585  .need_48MHz = true,
586  },
587  [STM32F446] = {
588  .family = STM32F4,
589  .max_coreclock = 180000000U,
590  .max_apb1 = 45000000U,
591  .max_apb2 = 90000000U,
592  .hsi = 16000000U,
593  .pll = stm32f4_7_pll_cfg,
594  .has_pll_i2s = true,
595  .has_pll_sai = true,
596  .has_pll_i2s_m = true,
597  .has_pll_sai_m = true,
598  .has_pll_i2s_alt_input = false,
599  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
600  .need_48MHz = true,
601  },
602  [STM32F469 ... STM32F479] = {
603  .family = STM32F4,
604  .max_coreclock = 180000000U,
605  .max_apb1 = 45000000U,
606  .max_apb2 = 90000000U,
607  .hsi = 16000000U,
608  .pll = stm32f4_7_pll_cfg,
609  .has_pll_i2s = true,
610  .has_pll_sai = true,
611  .has_pll_i2s_m = false,
612  .has_pll_sai_m = false,
613  .has_pll_i2s_alt_input = false,
614  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
615  .need_48MHz = true,
616  },
617  [STM32F722 ... STM32F779] = {
618  .family = STM32F7,
619  .max_coreclock = 216000000U,
620  .max_apb1 = 54000000U,
621  .max_apb2 = 108000000U,
622  .hsi = 16000000U,
623  .pll = stm32f4_7_pll_cfg,
624  .has_pll_i2s = true,
625  .has_pll_sai = true,
626  .has_pll_i2s_m = false,
627  .has_pll_sai_m = false,
628  .has_pll_i2s_alt_input = false,
629  .has_alt_48MHz = ALT_48MHZ_SAI | ALT_48MHZ_P,
630  .need_48MHz = true,
631  },
632 };
633 
637 static const clk_cfg_t stm32_mp_clk_cfg[] = {
638  [STM32MP157] = {
639  .family = STM32MP1,
640  .max_coreclock = 209000000U,
641  .max_apb1 = 104500000U,
642  .max_apb2 = 104500000U,
643  .max_apb3 = 104500000U,
644  .hsi = 64000000U,
645  .pll = stm32mp1_pll_cfg,
646  .has_pll_i2s = false,
647  .has_pll_sai = false,
648  .has_pll_i2s_m = false,
649  .has_pll_sai_m = false,
650  .has_pll_i2s_alt_input = false,
651  .has_alt_48MHz = 0,
652  .need_48MHz = true,
653  },
654 };
655 
656 #ifdef __cplusplus
657 }
658 #endif
659 
660 #endif /* CLK_CONF_H */
pll_cfg_t::max_q
unsigned max_q
Max Q.
Definition: clk_conf.h:165
clk_cfg_t::hsi
unsigned hsi
HSI frequency.
Definition: clk_conf.h:180
clk_cfg_t::max_apb2
unsigned max_apb2
Max APB2 clock.
Definition: clk_conf.h:177
clk_cfg_t::has_pll_sai
bool has_pll_sai
PLL SAI available.
Definition: clk_conf.h:185
clk_cfg_t::has_pll_sai_m
bool has_pll_sai_m
PLL SAI has a M factor.
Definition: clk_conf.h:187
clk_cfg_t::max_coreclock
unsigned max_coreclock
Max coreclock.
Definition: clk_conf.h:175
clk_cfg_t::has_alt_48MHz
int has_alt_48MHz
48MHz can be generated by an alternate source
Definition: clk_conf.h:192
pll_cfg_t::min_vco_input
unsigned min_vco_input
Min VCO input.
Definition: clk_conf.h:147
pll_cfg_t::max_n
unsigned max_n
Max N.
Definition: clk_conf.h:153
pll_cfg_t::max_vco_input
unsigned max_vco_input
Max VCO input.
Definition: clk_conf.h:148
pll_cfg_t::inc_q
unsigned inc_q
Increment between two values of Q.
Definition: clk_conf.h:166
pll_cfg_t::inc_p
unsigned inc_p
Increment between two values of P.
Definition: clk_conf.h:162
clk_cfg_t::need_48MHz
bool need_48MHz
48MHz is needed
Definition: clk_conf.h:193
pll_cfg_t
PLL configuration parameters.
Definition: clk_conf.h:146
clk_cfg_t::has_pll_i2s
bool has_pll_i2s
PLL I2S available.
Definition: clk_conf.h:184
pll_cfg_t::min_p
unsigned min_p
Min P.
Definition: clk_conf.h:160
pll_cfg_t::max_p
unsigned max_p
Max P.
Definition: clk_conf.h:161
clk_cfg_t::max_apb3
unsigned max_apb3
Max APB3 clock.
Definition: clk_conf.h:178
pll_cfg_t::inc_n
unsigned inc_n
Increment between two values of N.
Definition: clk_conf.h:154
pll_cfg_t::min_vco_output
unsigned min_vco_output
Min VCO output.
Definition: clk_conf.h:149
clk_cfg_t::family
enum fam family
Family.
Definition: clk_conf.h:173
pll_cfg_t::min_q
unsigned min_q
Min Q.
Definition: clk_conf.h:164
clk_cfg_t::has_pll_i2s_alt_input
bool has_pll_i2s_alt_input
PLL I2S has an external input available.
Definition: clk_conf.h:188
clk_cfg_t::has_pll_i2s_m
bool has_pll_i2s_m
PLL I2S has a M factor.
Definition: clk_conf.h:186
clk_cfg_t
Clock configuration.
Definition: clk_conf.h:172
pll_cfg_t::inc_m
unsigned inc_m
Increment between two values of M.
Definition: clk_conf.h:158
clk_cfg_t::max_apb1
unsigned max_apb1
Max APB1 clock.
Definition: clk_conf.h:176
pll_cfg_t::max_m
unsigned max_m
Max M.
Definition: clk_conf.h:157
pll_cfg_t::min_m
unsigned min_m
Min M.
Definition: clk_conf.h:156
clk_cfg_t::pll
pll_cfg_t pll
PLL configuration.
Definition: clk_conf.h:182
pll_cfg_t::min_n
unsigned min_n
Min N.
Definition: clk_conf.h:152
clk_cfg_t::hsi_prediv
unsigned hsi_prediv
Value if HSI has a fixed prediv, 0 otherwise.
Definition: clk_conf.h:190
pll_cfg_t::max_vco_output
unsigned max_vco_output
Max VCO output.
Definition: clk_conf.h:150