lis3dh.h

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/*
 * Copyright (C) 2015 Eistec AB
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef LIS3DH_H
#define LIS3DH_H
 
#include <stdint.h>
 
#include "periph/spi.h"
#include "periph/gpio.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define LIS3DH_WHO_AM_I_RESPONSE                 (0x33)
 
#define LIS3DH_REG_STATUS_AUX                    (0x07)
#define LIS3DH_REG_OUT_AUX_ADC1_L                (0x08)
#define LIS3DH_REG_OUT_AUX_ADC1_H                (0x09)
#define LIS3DH_REG_OUT_AUX_ADC2_L                (0x0A)
#define LIS3DH_REG_OUT_AUX_ADC2_H                (0x0B)
#define LIS3DH_REG_OUT_AUX_ADC3_L                (0x0C)
#define LIS3DH_REG_OUT_AUX_ADC3_H                (0x0D)
#define LIS3DH_REG_INT_COUNTER_REG               (0x0E)
#define LIS3DH_REG_WHO_AM_I                      (0x0F)
#define LIS3DH_REG_TEMP_CFG_REG                  (0x1F)
#define LIS3DH_REG_CTRL_REG1                     (0x20)
#define LIS3DH_REG_CTRL_REG2                     (0x21)
#define LIS3DH_REG_CTRL_REG3                     (0x22)
#define LIS3DH_REG_CTRL_REG4                     (0x23)
#define LIS3DH_REG_CTRL_REG5                     (0x24)
#define LIS3DH_REG_CTRL_REG6                     (0x25)
#define LIS3DH_REG_REFERENCE                     (0x26)
#define LIS3DH_REG_STATUS_REG                    (0x27)
#define LIS3DH_REG_OUT_X_L                       (0x28)
#define LIS3DH_REG_OUT_X_H                       (0x29)
#define LIS3DH_REG_OUT_Y_L                       (0x2A)
#define LIS3DH_REG_OUT_Y_H                       (0x2B)
#define LIS3DH_REG_OUT_Z_L                       (0x2C)
#define LIS3DH_REG_OUT_Z_H                       (0x2D)
#define LIS3DH_REG_FIFO_CTRL_REG                 (0x2E)
#define LIS3DH_REG_FIFO_SRC_REG                  (0x2F)
#define LIS3DH_REG_INT1_CFG                      (0x30)
#define LIS3DH_REG_INT1_SOURCE                   (0x31)
#define LIS3DH_REG_INT1_THS                      (0x32)
#define LIS3DH_REG_INT1_DURATION                 (0x33)
#define LIS3DH_REG_CLICK_CFG                     (0x38)
#define LIS3DH_REG_CLICK_SRC                     (0x39)
#define LIS3DH_REG_CLICK_THS                     (0x3A)
#define LIS3DH_REG_TIME_LIMIT                    (0x3B)
#define LIS3DH_REG_TIME_LATENCY                  (0x3C)
#define LIS3DH_REG_TIME_WINDOW                   (0x3D)
 
/*
 * Bit offsets within the individual registers
 * source: LIS3DH datasheet
 */
 
#define LIS3DH_TEMP_CFG_REG_ADC_PD_MASK          (1 << 7)
 
#define LIS3DH_TEMP_CFG_REG_TEMP_EN_MASK         (1 << 6)
 /* TEMP_CFG_REG bitfield macros */
 
#define LIS3DH_CTRL_REG1_ODR_SHIFT               (4)
 
#define LIS3DH_CTRL_REG1_ODR3_MASK               (1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 3))
 
#define LIS3DH_CTRL_REG1_ODR2_MASK               (1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 2))
 
#define LIS3DH_CTRL_REG1_ODR1_MASK               (1 << (LIS3DH_CTRL_REG1_ODR_SHIFT + 1))
 
#define LIS3DH_CTRL_REG1_ODR0_MASK               (1 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_CTRL_REG1_ODR_MASK                (LIS3DH_CTRL_REG1_ODR3_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR2_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR1_MASK | \
                                                  LIS3DH_CTRL_REG1_ODR0_MASK)
 
#define LIS3DH_CTRL_REG1_LPEN_MASK               (1 << 3)
 
#define LIS3DH_CTRL_REG1_ZEN_SHIFT               (2)
 
#define LIS3DH_CTRL_REG1_ZEN_MASK                (1 << LIS3DH_CTRL_REG1_ZEN_SHIFT)
 
#define LIS3DH_CTRL_REG1_YEN_SHIFT               (1)
 
#define LIS3DH_CTRL_REG1_YEN_MASK                (1 << LIS3DH_CTRL_REG1_YEN_SHIFT)
 
#define LIS3DH_CTRL_REG1_XEN_SHIFT               (0)
 
#define LIS3DH_CTRL_REG1_XEN_MASK                (1 << LIS3DH_CTRL_REG1_XEN_SHIFT)
 
#define LIS3DH_CTRL_REG1_XYZEN_SHIFT             (0)
 
#define LIS3DH_CTRL_REG1_XYZEN_MASK              (LIS3DH_CTRL_REG1_XEN_MASK | \
                                                  LIS3DH_CTRL_REG1_YEN_MASK | LIS3DH_CTRL_REG1_ZEN_MASK)
 
#define LIS3DH_AXES_X                            (LIS3DH_CTRL_REG1_XEN_MASK)
 
#define LIS3DH_AXES_Y                            (LIS3DH_CTRL_REG1_YEN_MASK)
 
#define LIS3DH_AXES_Z                            (LIS3DH_CTRL_REG1_ZEN_MASK)
  /* CTRL_REG1 bitfield macros */
 
#define LIS3DH_AXES_XYZ (LIS3DH_CTRL_REG1_XYZEN_MASK)
 
#define LIS3DH_CTRL_REG2_HPM1_MASK               (1 << 7)
 
#define LIS3DH_CTRL_REG2_HPM0_MASK               (1 << 6)
 
#define LIS3DH_CTRL_REG2_HPCF2_MASK              (1 << 5)
 
#define LIS3DH_CTRL_REG2_HPCF1_MASK              (1 << 4)
 
#define LIS3DH_CTRL_REG2_FDS_MASK                (1 << 3)
 
#define LIS3DH_CTRL_REG2_HPCLICK_MASK            (1 << 2)
 
#define LIS3DH_CTRL_REG2_HPIS2_MASK              (1 << 1)
 
#define LIS3DH_CTRL_REG2_HPIS1_MASK              (1 << 0)
 /* CTRL_REG2 bitfield macros */
 
#define LIS3DH_CTRL_REG3_I1_CLICK_MASK           (1 << 7)
 
#define LIS3DH_CTRL_REG3_I1_AOI1_MASK            (1 << 6)
 
#define LIS3DH_CTRL_REG3_I1_AOI2_MASK            (1 << 5)
 
#define LIS3DH_CTRL_REG3_I1_DRDY1_MASK           (1 << 4)
 
#define LIS3DH_CTRL_REG3_I1_DRDY2_MASK           (1 << 3)
 
#define LIS3DH_CTRL_REG3_I1_WTM_MASK             (1 << 2)
 
#define LIS3DH_CTRL_REG3_I1_OVERRUN_MASK         (1 << 1)
 /* CTRL_REG3 bitfield macros */
 
#define LIS3DH_CTRL_REG4_BDU_MASK                (1 << 7)
 
#define LIS3DH_CTRL_REG4_BDU_ENABLE              (LIS3DH_CTRL_REG4_BDU_MASK)
 
#define LIS3DH_CTRL_REG4_BDU_DISABLE             (0)
 
#define LIS3DH_CTRL_REG4_BLE_MASK                (1 << 6)
 
#define LIS3DH_CTRL_REG4_BLE_LITTLE_ENDIAN       (0)
 
#define LIS3DH_CTRL_REG4_BLE_BIG_ENDIAN          (LIS3DH_CTRL_REG4_BLE_MASK)
 
#define LIS3DH_CTRL_REG4_FS1_MASK                (1 << 5)
 
#define LIS3DH_CTRL_REG4_FS0_MASK                (1 << 4)
 
#define LIS3DH_CTRL_REG4_FS_MASK                 (LIS3DH_CTRL_REG4_FS1_MASK | \
                                                  LIS3DH_CTRL_REG4_FS0_MASK)
 
#define LIS3DH_CTRL_REG4_SCALE_2G                (0)
 
#define LIS3DH_CTRL_REG4_SCALE_4G                (LIS3DH_CTRL_REG4_FS0_MASK)
 
#define LIS3DH_CTRL_REG4_SCALE_8G                (LIS3DH_CTRL_REG4_FS1_MASK)
 
#define LIS3DH_CTRL_REG4_SCALE_16G               (LIS3DH_CTRL_REG4_FS1_MASK | LIS3DH_CTRL_REG4_FS0_MASK)
 
#define LIS3DH_CTRL_REG4_HR_MASK                 (1 << 3)
 
#define LIS3DH_CTRL_REG4_ST1_MASK                (1 << 2)
 
#define LIS3DH_CTRL_REG4_ST0_MASK                (1 << 1)
 
#define LIS3DH_CTRL_REG4_SIM_MASK                (1 << 0)
 
#define LIS3DH_CTRL_REG5_REBOOT_MASK             (1 << 7)
 
#define LIS3DH_CTRL_REG5_FIFO_EN_MASK            (1 << 6)
 
#define LIS3DH_CTRL_REG5_LIR_I1_MASK             (1 << 3)
 
#define LIS3DH_CTRL_REG5_D4D_I1_MASK             (1 << 2)
 /* CTRL_REG4 bitfield macros */
 
#define LIS3DH_STATUS_REG_ZYXOR_MASK             (1 << 7)
 
#define LIS3DH_STATUS_REG_ZOR_MASK               (1 << 6)
 
#define LIS3DH_STATUS_REG_YOR_MASK               (1 << 5)
 
#define LIS3DH_STATUS_REG_XOR_MASK               (1 << 4)
 
#define LIS3DH_STATUS_REG_ZYXDA_MASK             (1 << 3)
 
#define LIS3DH_STATUS_REG_ZDA_MASK               (1 << 2)
 
#define LIS3DH_STATUS_REG_YDA_MASK               (1 << 1)
 
#define LIS3DH_STATUS_REG_XDA_MASK               (1 << 0)
 /* STATUS_REG bitfield macros */
 
#define LIS3DH_FIFO_CTRL_REG_FM_SHIFT            (6)
#define LIS3DH_FIFO_CTRL_REG_FM1_MASK            (1 << 7)
#define LIS3DH_FIFO_CTRL_REG_FM0_MASK            (1 << 6)
#define LIS3DH_FIFO_CTRL_REG_FM_MASK             (LIS3DH_FIFO_CTRL_REG_FM1_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FM0_MASK)
#define LIS3DH_FIFO_CTRL_REG_TR_MASK             (1 << 5)
#define LIS3DH_FIFO_CTRL_REG_FTH4_MASK           (1 << 4)
#define LIS3DH_FIFO_CTRL_REG_FTH3_MASK           (1 << 3)
#define LIS3DH_FIFO_CTRL_REG_FTH2_MASK           (1 << 2)
#define LIS3DH_FIFO_CTRL_REG_FTH1_MASK           (1 << 1)
#define LIS3DH_FIFO_CTRL_REG_FTH0_MASK           (1 << 0)
#define LIS3DH_FIFO_CTRL_REG_FTH_SHIFT           (0)
#define LIS3DH_FIFO_CTRL_REG_FTH_MASK            (LIS3DH_FIFO_CTRL_REG_FTH0_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH1_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH2_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH3_MASK | \
                                                  LIS3DH_FIFO_CTRL_REG_FTH4_MASK)
 /* FIFO_CTRL_REG bitfield macros */
 
#define LIS3DH_FIFO_SRC_REG_WTM_MASK             (1 << 7)
#define LIS3DH_FIFO_SRC_REG_OVRN_FIFO_MASK       (1 << 6)
#define LIS3DH_FIFO_SRC_REG_EMPTY_MASK           (1 << 5)
#define LIS3DH_FIFO_SRC_REG_FSS4_MASK            (1 << 4)
#define LIS3DH_FIFO_SRC_REG_FSS3_MASK            (1 << 3)
#define LIS3DH_FIFO_SRC_REG_FSS2_MASK            (1 << 2)
#define LIS3DH_FIFO_SRC_REG_FSS1_MASK            (1 << 1)
#define LIS3DH_FIFO_SRC_REG_FSS0_MASK            (1 << 0)
#define LIS3DH_FIFO_SRC_REG_FSS_SHIFT            (0)
#define LIS3DH_FIFO_SRC_REG_FSS_MASK             (LIS3DH_FIFO_SRC_REG_FSS0_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS1_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS2_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS3_MASK | \
                                                  LIS3DH_FIFO_SRC_REG_FSS4_MASK)
 /* FIFO_CTRL_REG bitfield macros */
 
#define LIS3DH_SPI_WRITE_MASK                    (0 << 7)
 
#define LIS3DH_SPI_READ_MASK                     (1 << 7)
 
#define LIS3DH_SPI_MULTI_MASK                    (1 << 6)
 
#define LIS3DH_SPI_SINGLE_MASK                   (0 << 6)
 
#define LIS3DH_SPI_ADDRESS_MASK                  (0x3F)
 /* Register address bitfield macros */
 
#define LIS3DH_ADC_DATA_SIZE                     (2U)
 
#define LIS3DH_FIFO_MODE_BYPASS                  (0x00 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
 
#define LIS3DH_FIFO_MODE_FIFO                    (0x01 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
 
#define LIS3DH_FIFO_MODE_STREAM                  (0x02 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
 
#define LIS3DH_FIFO_MODE_STREAM_TO_FIFO          (0x03 << LIS3DH_FIFO_CTRL_REG_FM_SHIFT)
 
#define LIS3DH_ODR_POWERDOWN                     (0x00 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_1Hz                           (0x01 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_10Hz                          (0x02 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_25Hz                          (0x03 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_50Hz                          (0x04 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_100Hz                         (0x05 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_200Hz                         (0x06 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_400Hz                         (0x07 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_LP1600Hz                      (0x08 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_NP1250Hz                      (0x09 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
#define LIS3DH_ODR_LP5000HZ                      (0x09 << LIS3DH_CTRL_REG1_ODR_SHIFT)
 
typedef struct {
    spi_t spi;              
    spi_clk_t clk;          
    gpio_t cs;              
    gpio_t int1;            
    gpio_t int2;            
    uint8_t scale;          
    uint8_t odr;            
} lis3dh_params_t;
 
typedef struct {
    lis3dh_params_t params; 
    uint16_t scale;         
} lis3dh_t;
 
typedef struct __attribute__((packed))
{
    int16_t acc_x;          
    int16_t acc_y;          
    int16_t acc_z;          
} lis3dh_data_t;
 
int lis3dh_init(lis3dh_t *dev, const lis3dh_params_t *params);
 
int lis3dh_read_xyz(const lis3dh_t *dev, lis3dh_data_t *acc_data);
 
int lis3dh_read_aux_adc1(const lis3dh_t *dev, int16_t *out);
 
int lis3dh_read_aux_adc2(const lis3dh_t *dev, int16_t *out);
 
int lis3dh_read_aux_adc3(const lis3dh_t *dev, int16_t *out);
 
int lis3dh_set_aux_adc(const lis3dh_t *dev, const uint8_t enable, const uint8_t temperature);
 
int lis3dh_set_axes(const lis3dh_t *dev, const uint8_t axes);
 
int lis3dh_set_fifo(const lis3dh_t *dev, const uint8_t mode, const uint8_t watermark);
 
int lis3dh_set_odr(const lis3dh_t *dev, const uint8_t odr);
 
int lis3dh_set_scale(lis3dh_t *dev, const uint8_t scale);
 
int lis3dh_set_int1(const lis3dh_t *dev, const uint8_t mode);
 
int lis3dh_get_fifo_level(const lis3dh_t *dev);
 
#ifdef __cplusplus
}
#endif
 
#endif /* LIS3DH_H */