mtd_spi_nor.h
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1 /*
2  * Copyright (C) 2016 Eistec AB
3  * 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
24 #ifndef MTD_SPI_NOR_H
25 #define MTD_SPI_NOR_H
26 
27 #include <stdint.h>
28 
29 #include "periph_conf.h"
30 #include "periph/spi.h"
31 #include "periph/gpio.h"
32 #include "mtd.h"
33 
34 #ifdef __cplusplus
35 extern "C"
36 {
37 #endif
38 
42 typedef struct {
43  uint8_t rdid;
44  uint8_t wren;
45  uint8_t rdsr;
46  uint8_t wrsr;
47  uint8_t read;
48  uint8_t read_fast;
49  uint8_t page_program;
50  uint8_t sector_erase;
51  uint8_t block_erase_32k;
52  uint8_t block_erase_64k;
53  uint8_t chip_erase;
54  uint8_t sleep;
55  uint8_t wake;
56  /* TODO: enter 4 byte address mode for large memories */
58 
64 typedef struct __attribute__((packed)) {
65  uint8_t bank;
66  uint8_t manuf;
67  uint8_t device[2];
69 
75 #define JEDEC_NEXT_BANK (0x7f)
76 
82 #define JEDEC_BANK_MAX (10)
83 
87 #define SPI_NOR_F_SECT_4K (1)
88 
92 #define SPI_NOR_F_SECT_32K (2)
93 
97 #define SPI_NOR_F_SECT_64K (4)
98 
102 typedef struct {
104  uint32_t wait_chip_erase;
105  uint32_t wait_64k_erase;
106  uint32_t wait_32k_erase;
107  uint32_t wait_sector_erase;
108  uint32_t wait_chip_wake_up;
110  uint16_t flag;
113  gpio_t cs;
114  gpio_t wp;
115  gpio_t hold;
116  uint8_t addr_width;
118 
124 typedef struct {
134  uint32_t page_addr_mask;
140  uint32_t sec_addr_mask;
152  uint8_t sec_addr_shift;
153 } mtd_spi_nor_t;
154 
158 extern const mtd_desc_t mtd_spi_nor_driver;
159 
160 /* Available opcode tables for known devices */
161 /* Defined in mtd_spi_nor_configs.c */
170 
177 
178 #ifdef __cplusplus
179 }
180 #endif
181 
182 #endif /* MTD_SPI_NOR_H */
183 
mtd_spi_nor_opcode_t::rdsr
uint8_t rdsr
Read status register.
Definition: mtd_spi_nor.h:45
mtd_dev_t
MTD device descriptor.
Definition: mtd.h:58
mtd_spi_nor_t::page_addr_shift
uint8_t page_addr_shift
number of right shifts to get the address to the start of the page
Definition: mtd_spi_nor.h:146
mtd_spi_nor_params_t::mode
spi_mode_t mode
SPI mode.
Definition: mtd_spi_nor.h:112
mtd_spi_nor_params_t::opcode
const mtd_spi_nor_opcode_t * opcode
Opcode table for the device.
Definition: mtd_spi_nor.h:103
mtd_spi_nor_opcode_t::wake
uint8_t wake
Release from deep power down.
Definition: mtd_spi_nor.h:55
mtd_spi_nor_t::jedec_id
mtd_jedec_id_t jedec_id
JEDEC ID of the chip.
Definition: mtd_spi_nor.h:127
mtd_spi_nor_params_t::wait_32k_erase
uint32_t wait_32k_erase
32KB page erase wait time in µs
Definition: mtd_spi_nor.h:106
spi.h
Low-level SPI peripheral driver interface definition.
mtd_spi_nor_params_t::wait_64k_erase
uint32_t wait_64k_erase
64KB page erase wait time in µs
Definition: mtd_spi_nor.h:105
mtd_spi_nor_t::sec_addr_shift
uint8_t sec_addr_shift
number of right shifts to get the address to the start of the sector
Definition: mtd_spi_nor.h:152
mtd_spi_nor_opcode_t::read
uint8_t read
Read data bytes, 3 byte address.
Definition: mtd_spi_nor.h:47
mtd_jedec_id_t::manuf
uint8_t manuf
Manufacturer ID, 1 byte.
Definition: mtd_spi_nor.h:66
mtd_spi_nor_opcode_t::wren
uint8_t wren
Write enable.
Definition: mtd_spi_nor.h:44
mtd_spi_nor_opcode_t
SPI NOR flash opcode table.
Definition: mtd_spi_nor.h:42
mtd_desc
MTD driver interface.
Definition: mtd.h:75
spi_mode_t
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
mtd_spi_nor_opcode_t::block_erase_32k
uint8_t block_erase_32k
32KiB block erase
Definition: mtd_spi_nor.h:51
mtd_spi_nor_opcode_t::page_program
uint8_t page_program
Page program.
Definition: mtd_spi_nor.h:49
mtd_spi_nor_opcode_t::read_fast
uint8_t read_fast
Read data bytes, 3 byte address, at higher speed.
Definition: mtd_spi_nor.h:48
mtd_spi_nor_params_t::wp
gpio_t wp
Write Protect pin GPIO handle.
Definition: mtd_spi_nor.h:114
mtd_spi_nor_params_t::wait_sector_erase
uint32_t wait_sector_erase
4KB sector erase wait time in µs
Definition: mtd_spi_nor.h:107
mtd_spi_nor_params_t::wait_chip_erase
uint32_t wait_chip_erase
Full chip erase wait time in µs.
Definition: mtd_spi_nor.h:104
mtd_spi_nor_opcode_default_4bytes
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default_4bytes
Default 4-byte addresses opcodes.
mtd_spi_nor_params_t::flag
uint16_t flag
Config flags.
Definition: mtd_spi_nor.h:110
spi_clk_t
spi_clk_t
Available SPI clock speeds.
Definition: spi.h:173
mtd_spi_nor_t::base
mtd_dev_t base
inherit from mtd_dev_t object
Definition: mtd_spi_nor.h:125
mtd_spi_nor_params_t::spi
spi_t spi
SPI bus the device is connected to.
Definition: mtd_spi_nor.h:111
mtd_spi_nor_opcode_t::wrsr
uint8_t wrsr
Write status register.
Definition: mtd_spi_nor.h:46
mtd_spi_nor_opcode_t::rdid
uint8_t rdid
Read identification (JEDEC ID)
Definition: mtd_spi_nor.h:43
mtd_spi_nor_opcode_t::sleep
uint8_t sleep
Deep power down.
Definition: mtd_spi_nor.h:54
mtd_spi_nor_params_t::wait_chip_wake_up
uint32_t wait_chip_wake_up
Chip wake up time in µs.
Definition: mtd_spi_nor.h:108
mtd_spi_nor_params_t
Compile-time parameters for a serial flash device.
Definition: mtd_spi_nor.h:102
mtd_spi_nor_params_t::addr_width
uint8_t addr_width
Number of bytes in addresses, usually 3 for small devices.
Definition: mtd_spi_nor.h:116
mtd_jedec_id_t
Internal representation of JEDEC memory ID codes.
Definition: mtd_spi_nor.h:64
mtd.h
gpio.h
Low-level GPIO peripheral driver interface definitions.
mtd_spi_nor_t::page_addr_mask
uint32_t page_addr_mask
bitmask to corresponding to the page address
Definition: mtd_spi_nor.h:134
mtd_spi_nor_t
Device descriptor for serial flash memory devices.
Definition: mtd_spi_nor.h:124
mtd_spi_nor_opcode_t::chip_erase
uint8_t chip_erase
Chip erase.
Definition: mtd_spi_nor.h:53
mtd_spi_nor_params_t::clk
spi_clk_t clk
SPI clock.
Definition: mtd_spi_nor.h:109
mtd_spi_nor_driver
const mtd_desc_t mtd_spi_nor_driver
NOR flash SPI MTD device operations table.
mtd_spi_nor_params_t::hold
gpio_t hold
HOLD pin GPIO handle.
Definition: mtd_spi_nor.h:115
mtd_spi_nor_t::sec_addr_mask
uint32_t sec_addr_mask
bitmask to corresponding to the sector address
Definition: mtd_spi_nor.h:140
mtd_spi_nor_params_t::cs
gpio_t cs
CS pin GPIO handle.
Definition: mtd_spi_nor.h:113
mtd_spi_nor_opcode_default
const mtd_spi_nor_opcode_t mtd_spi_nor_opcode_default
Default command opcodes.
mtd_spi_nor_opcode_t::block_erase_64k
uint8_t block_erase_64k
Block erase (usually 64 KiB)
Definition: mtd_spi_nor.h:52
mtd_spi_nor_opcode_t::sector_erase
uint8_t sector_erase
Block erase 4 KiB.
Definition: mtd_spi_nor.h:50
mtd_jedec_id_t::bank
uint8_t bank
Manufacturer ID bank number, 1 through 10, see JEP106.
Definition: mtd_spi_nor.h:65
mtd_spi_nor_t::params
const mtd_spi_nor_params_t * params
SPI NOR params.
Definition: mtd_spi_nor.h:126
spi_t
unsigned int spi_t
Default type for SPI devices.
Definition: spi.h:118