cpu.h

Go to the documentation of this file.

/*
 * Copyright (C) 2015 Kaspar Schleiser <kaspar@schleiser.de>
 *               2014 Freie Universität Berlin, Hinnerk van Bruinehsen
 *               2018 RWTH Aachen, Josua Arndt <jarndt@ias.rwth-aachen.de>
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef CPU_H
#define CPU_H
 
#include <stdio.h>
#include <stdint.h>
 
#include <avr/interrupt.h>
#include "cpu_conf.h"
#include "sched.h"
#include "thread.h"
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#define PERIPH_I2C_NEED_READ_REG
#define PERIPH_I2C_NEED_WRITE_REG
#define PERIPH_I2C_NEED_READ_REGS
#define PERIPH_I2C_NEED_WRITE_REGS
 
#define ATMEGA_STATE_FLAG_ISR           (0x80U) 
#define ATMEGA_STATE_FLAG_UART0_TX      (0x01U) 
#define ATMEGA_STATE_FLAG_UART1_TX      (0x02U) 
#define ATMEGA_STATE_FLAG_UART_TX(x)    (0x01U << x) 
extern uint8_t atmega_state;
 
static inline uint8_t atmega_get_state(void)
{
    uint8_t state;
    __asm__ volatile(
        "lds   %[state], atmega_state       \n\t"
        : [state]   "=r" (state)
        :
        : "memory"
 
    );
 
    return state;
}
 
static inline void atmega_enter_isr(void)
{
    /* This flag is only called from IRQ context, and nested IRQs are not
     * supported as of now. The flag will be unset before the IRQ context is
     * left, so no need to use memory barriers or atomics here
     */
    atmega_state |= ATMEGA_STATE_FLAG_ISR;
}
 
static inline int atmega_is_uart_tx_pending(void)
{
    uint8_t state = atmega_get_state();
    return (state & (ATMEGA_STATE_FLAG_UART0_TX | ATMEGA_STATE_FLAG_UART1_TX));
}
 
void atmega_exit_isr(void);
 
void cpu_init(void);
 
static inline void __attribute__((always_inline)) cpu_print_last_instruction(void)
{
    uint8_t hi;
    uint8_t lo;
    uint16_t ptr;
 
    __asm__ volatile ("in __tmp_reg__, __SP_H__  \n\t"
                      "mov %0, __tmp_reg__       \n\t"
                      : "=g" (hi));
 
    __asm__ volatile ("in __tmp_reg__, __SP_L__  \n\t"
                      "mov %0, __tmp_reg__       \n\t"
                      : "=g" (lo));
    ptr = hi << 8 | lo;
    printf("Stack Pointer: 0x%04x\n", ptr);
}
 
enum {
    CPU_ATMEGA_CLK_SCALE_DIV1   = 0,
    CPU_ATMEGA_CLK_SCALE_DIV2   = 1,
    CPU_ATMEGA_CLK_SCALE_DIV4   = 2,
    CPU_ATMEGA_CLK_SCALE_DIV8   = 3,
    CPU_ATMEGA_CLK_SCALE_DIV16  = 4,
    CPU_ATMEGA_CLK_SCALE_DIV32  = 5,
    CPU_ATMEGA_CLK_SCALE_DIV64  = 6,
    CPU_ATMEGA_CLK_SCALE_DIV128 = 7,
    CPU_ATMEGA_CLK_SCALE_DIV256 = 8,
    CPU_ATMEGA_CLK_SCALE_DIV512 = 9,
};
 
static inline void atmega_set_prescaler(uint8_t clk_scale)
{
    /* Enable clock change */
    /* Must be assignment to set all other bits to zero, see datasheet */
    CLKPR = (1 << CLKPCE);
 
    /* Write clock within 4 cycles */
    CLKPR = clk_scale;
}
 
void atmega_stdio_init(void);
 
#ifdef __cplusplus
}
#endif
 
#endif /* CPU_H */