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periph_conf.h
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/*
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* Copyright (C) 2016 Nicholas Jackson
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* 2017 HAW Hamburg
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* 2020 Locha Inc
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* the main clock is fixed to 48MHZ */
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#define CLOCK_CORECLOCK (48000000U)
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static
const
timer_conf_t
timer_config[] = {
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{
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.
cfg
= GPT_CFG_16T,
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.chn = 2,
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},
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{
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.cfg =
GPT_CFG_32T
,
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.chn = 1,
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},
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{
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.cfg = GPT_CFG_16T,
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.chn = 2,
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},
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{
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.cfg =
GPT_CFG_32T
,
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.chn = 1,
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}
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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static
const
uart_conf_t
uart_config[] = {
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{
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.regs =
UART0
,
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.tx_pin = 3,
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.rx_pin = 2,
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#ifdef MODULE_PERIPH_UART_HW_FC
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.rts_pin = 18,
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.cts_pin = 19,
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#endif
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.intn =
UART0_IRQN
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},
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{
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.regs =
UART1
,
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.tx_pin = 11,
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.rx_pin = 12,
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#ifdef MODULE_PERIPH_UART_HW_FC
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.rts_pin = 8,
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.cts_pin = 9,
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#endif
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.intn = UART1_IRQN
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}
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};
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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#define I2C_NUMOF (1)
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#define I2C_SCL_PIN (4)
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#define I2C_SDA_PIN (5)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* PERIPH_CONF_H */
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GPT_CFG_32T
#define GPT_CFG_32T
GPT register values.
Definition:
cc26xx_cc13xx_gpt.h:89
UART0
#define UART0
UART0 register bank.
Definition:
cc26xx_cc13xx_uart.h:134
UART0_IRQN
@ UART0_IRQN
21 UART0 Rx and Tx
Definition:
cc26xx_cc13xx.h:78
uart_conf_t
UART device configuration.
Definition:
periph_cpu.h:166
timer_conf_t
Timer configuration.
Definition:
periph_cpu.h:288
timer_conf_t::cfg
uint_fast8_t cfg
timer config word
Definition:
periph_cpu.h:290
UART1
#define UART1
UART1 register bank.
Definition:
cc26xx_cc13xx_uart.h:138
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