periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 #include "cfg_clock_32_1.h"
25 #include "cfg_rtt_default.h"
26 #include "cfg_timer_default.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define UART_NUMOF (1U)
37 #define UART_PIN_RX GPIO_PIN(0, 11)
38 #define UART_PIN_TX GPIO_PIN(0, 5)
39 
45 static const spi_conf_t spi_config[] = {
46  {
47  .dev = NRF_SPIM0,
48  .sclk = GPIO_PIN(0, 4),
49  .mosi = GPIO_PIN(0, 5),
50  .miso = GPIO_PIN(0, 6),
51  .ppi = 0,
52  },
53  { /* Connected to the DWM1001 UWB transceiver */
54  .dev = NRF_SPIM1,
55  .sclk = GPIO_PIN(0, 16),
56  .mosi = GPIO_PIN(0, 20),
57  .miso = GPIO_PIN(0, 18),
58  .ppi = 0,
59  },
60 };
61 
62 #define SPI_NUMOF ARRAY_SIZE(spi_config)
63 
69 static const i2c_conf_t i2c_config[] = {
70  {
71  .dev = NRF_TWIM1,
72  .scl = GPIO_PIN(0, 28),
73  .sda = GPIO_PIN(0, 29),
74  .speed = I2C_SPEED_NORMAL
75  }
76 };
77 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
78 
83 #define NRF5X_ENABLE_DCDC
84 
85 #ifdef __cplusplus
86 }
87 #endif
88 
89 #endif /* PERIPH_CONF_H */
90 
cfg_clock_32_1.h
Common clock configuration for the nRF52 based boards.
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
i2c_conf_t::dev
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:247