cc26x0_prcm.h File Reference

CC26x0 PRCM register definitions. More...

Detailed Description

CC26x0 PRCM register definitions.

Definition in file cc26x0_prcm.h.

#include <cc26xx_cc13xx.h>

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Data Structures
struct	ddi0_osc_regs_t
	DDI_0_OSC registers. More...
struct	aon_sysctl_regs_t
	AON_SYSCTL registers. More...
struct	aon_wuc_regs_t
	AON_WUC registers. More...
struct	aon_rtc_regs_t
	AON_RTC registers. More...
struct	prcm_regs_t
	PRCM registers. More...

Macros
#define	AON_RTC   ((aon_rtc_regs_t *) (AON_RTC_BASE))
	AON_RTC register bank.
#define	DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask   0x6
	DDI_0_OSC register values.
#define	DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC   0x0
#define	DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC   0x4
#define	DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC   0x8
#define	DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC   0xC
#define	DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask   0x60
#define	DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF   0x00 /* 31.25kHz */
#define	DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF   0x20 /* 31.25kHz */
#define	DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF   0x40 /* 32kHz */
#define	DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF   0x60 /* 32.768kHz */
#define	DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask   0x180
#define	DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF   0x000 /* 48MHz */
#define	DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF   0x080 /* 48MHz */
#define	DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF   0x100 /* 24MHz */
#define	DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask   0x6000000
#define	DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL   0x10000000
#define	DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL   0x20000000
#define	DDI_0_OSC_CTL0_XTAL_IS_24M   0x80000000
#define	DDI0_OSC_BASE   0x400CA000
	DDI0_OSC base address.
#define	DDI_0_OSC   ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
	DDI_0_OSC register bank.
#define	AON_SYSCTL_BASE   0x40090000
	AON_SYSCTL base address.
#define	AON_SYSCTL   ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE))
	AON_SYSCTL register bank.
#define	MCUCLK_PWR_DWN_SRC   0x1 /* SCLK_LF in powerdown (no clock elsewise) */
	AON_WUC register values.
#define	MCUCLK_PWR_DWN_SRC_mask   0x3
#define	MCUCLK_RCOSC_HF_CAL_DONE   0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */
#define	AUXCLK_SRC_HF   0x1 /* SCLK for AUX */
#define	AUXCLK_SRC_LF   0x4
#define	AUXCLK_SRC_mask   0x7 /* guaranteed to be glitchless */
#define	AUXCLK_SCLK_HF_DIV_pos   8 /* don't set while SCLK_HF active for AUX */
#define	AUXCLK_SCLK_HF_DIV_mask   0x700 /* divisor will be 2^(value+1) */
#define	AUXCLK_PWR_DWN_SRC_pos   11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */
#define	AUXCLK_PWR_DWN_SRC_mask   0x1800 /* datasheet is confusing.. */
#define	MCUCFG_SRAM_RET_OFF   0x0 /* no retention for any SRAM-bank */
#define	MCUCFG_SRAM_RET_B0   0x1
#define	MCUCFG_SRAM_RET_B01   0x3
#define	MCUCFG_SRAM_RET_B012   0x7
#define	MCUCFG_SRAM_RET_B0124   0xF /* retention for banks 0, 1, 2, and 3 */
#define	MCUCFG_SRAM_FIXED_WU_EN   0x100
#define	MCUCFG_SRAM_VIRT_OFF   0x200
#define	AUXCFG_RAM_RET_EN   0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */
#define	AUXCTL_AUX_FORCE_ON   0x1
#define	AUXCTL_SWEV   0x2
#define	AUXCTL_SCE_RUN_EN   0x3
#define	AUXCTL_RESET_REQ   0x80000000
#define	PWRSTAT_AUX_RESET_DONE   0x2
#define	PWRSTAT_AUX_BUS_CONNECTED   0x4
#define	PWRSTAT_MCU_PD_ON   0x10
#define	PWRSTAT_AUX_PD_ON   0x20
#define	PWRSTAT_JTAG_PD_ON   0x40
#define	PWRSTAT_AUX_PWR_DNW   0x200
#define	SHUTDOWN_EN   0x1 /* register/cancel shutdown request */
#define	AONWUC_CTL0_MCU_SRAM_ERASE   0x4
#define	AONWUC_CTL0_AUX_SRAM_ERASE   0x8
#define	AONWUC_CTL0_PWR_DWN_DIS   0x10 /* disable powerdown on request */
#define	AONWUC_CTL1_MCU_WARM_RESET   0x1 /* last MCU reset was a warm reset */
#define	AONWUC_CTL1_MCU_RESET_SRC   0x2 /* JTAG was source of last reset (MCU SW elsewise) */
#define	RECHARGECFG_PER_E_mask   0x00000007 /* number of 32KHz clocks between activation of recharge controller: */
#define	RECHARGECFG_PER_M_mask   0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
#define	RECHARGECFG_MAX_PER_E_mask   0x00000700 /* maximum period the recharge algorithm can take */
#define	RECHARGECFG_MAX_PER_M_mask   0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */
#define	RECHARGECFG_C1_mask   0x000F0000 /* i resign */
#define	RECHARGECFG_C2_mask   0x000F0000
#define	RECHARGECFG_ADAPTIVE_EN   0x80000000
#define	RECHARGESTAT_MAX_USED_PER_mask   0x0FFFF
#define	RECHARGESTAT_VDDR_SMPLS_mask   0xF0000
#define	OSCCFG_PER_E_mask   0x07 /* number of 32KHz clocks between oscillator amplitude callibrations */
#define	OSCCFG_PER_M_mask   0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
#define	JTAGCFG_JTAG_PD_FORCE_ON   0x10
#define	AON_WUC_BASE   0x40091000
	AON_WUC base address.
#define	AON_WUC   ((aon_wuc_regs_t *) (AON_WUC_BASE))
	AON_WUC register bank.
#define	AON_RTC_CTL_RTC_UPD_EN   0x00000002
	RTC_UPD is a 16 KHz signal used to sync up the radio timer. More...
#define	AON_RTC_BASE   (PERIPH_BASE + 0x92000)
	AON_RTC base address.
#define	CLKLOADCTL_LOAD   0x1
	PRCM register values.
#define	CLKLOADCTL_LOADDONE   0x2
#define	PDCTL0_RFC_ON   0x1
#define	PDCTL0_SERIAL_ON   0x2
#define	PDCTL0_PERIPH_ON   0x4
#define	PDSTAT0_RFC_ON   0x1
#define	PDSTAT0_SERIAL_ON   0x2
#define	PDSTAT0_PERIPH_ON   0x4
#define	PDCTL1_CPU_ON   0x2
#define	PDCTL1_RFC_ON   0x4
#define	PDCTL1_VIMS_ON   0x8
#define	PDSTAT1_CPU_ON   0x2
#define	PDSTAT1_RFC_ON   0x4
#define	PDSTAT1_VIMS_ON   0x8
#define	GPIOCLKGR_CLK_EN   0x1
#define	I2CCLKGR_CLK_EN   0x1
#define	UARTCLKGR_CLK_EN_UART0   0x1
#define	GPIOCLKGS_CLK_EN   0x1
#define	I2CCLKGS_CLK_EN   0x1
#define	UARTCLKGS_CLK_EN_UART0   0x1
#define	GPIOCLKGDS_CLK_EN   0x1
#define	I2CCLKGDS_CLK_EN   0x1
#define	UARTCLKGDS_CLK_EN_UART0   0x1
#define	PRCM_BASE   (PERIPH_BASE + 0x82000)
	PRCM base address.
#define	PRCM_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x82000)
	PRCM base address (nonbuf)
#define	PRCM   ((prcm_regs_t *) (PRCM_BASE))
	PRCM register bank.
#define	PRCM_NONBUF   ((prcm_regs_t *) (PRCM_BASE_NONBUF))
	PRCM register bank (nonbuf)