TI CC26x0 peripheral memory map
CPU

Texas Instruments CC26x0 memory mappings for peripherals. More...

Detailed Description

Texas Instruments CC26x0 memory mappings for peripherals.

#define AUX_AIODIO0_BASE   0x400C1000
 AUX_AIODIO0 base address.
 
#define AUX_AIODIO1_BASE   0x400C2000
 AUX_AIODIO1 base address.
 
#define AUX_TDC_BASE   0x400C4000
 AUX_TDC base address.
 
#define AUX_EVCTL_BASE   0x400C5000
 AUX_EVCTL base address.
 
#define AUX_WUC_BASE   0x400C6000
 AUX_WUC base address.
 
#define AUX_TIMER_BASE   0x400C7000
 AUX_WUC base address.
 
#define AUX_SMPH_BASE   0x400C8000
 AUX_WUC base address.
 
#define AUX_ANAIF_BASE   0x400C9000
 AUX_WUC base address.
 
#define AUX_SMPH   ((aux_smph_regs_t *) (AUX_SMPH_BASE))
 AUX_SMPH register bank.
 
#define ADI_4_AUX_BASE   0x400CB000
 AUX_WUC base address.
 
#define FCFG_BASE   0x50001000
 base address of FCFG memory
 
#define FCFG   ((fcfg_regs_t *) (FCFG_BASE))
 FCFG register bank.
 
#define DDI0_OSC_BASE   0x400CA000
 DDI0_OSC base address.
 
#define AON_SYSCTL_BASE   0x40090000
 AON_SYSCTL base address.
 
#define DDI_0_OSC   ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
 DDI_0_OSC register bank.
 
#define AON_SYSCTL   ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE))
 AON_SYSCTL register bank.
 
#define MCUCLK_PWR_DWN_SRC   0x1 /* SCLK_LF in powerdown (no clock elsewise) */
 AON_WUC register values.
 
#define MCUCLK_PWR_DWN_SRC_mask   0x3
 
#define MCUCLK_RCOSC_HF_CAL_DONE   0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */
 
#define AUXCLK_SRC_HF   0x1 /* SCLK for AUX */
 
#define AUXCLK_SRC_LF   0x4
 
#define AUXCLK_SRC_mask   0x7 /* guaranteed to be glitchless */
 
#define AUXCLK_SCLK_HF_DIV_pos   8 /* don't set while SCLK_HF active for AUX */
 
#define AUXCLK_SCLK_HF_DIV_mask   0x700 /* divisor will be 2^(value+1) */
 
#define AUXCLK_PWR_DWN_SRC_pos   11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */
 
#define AUXCLK_PWR_DWN_SRC_mask   0x1800 /* datasheet is confusing.. */
 
#define MCUCFG_SRAM_RET_OFF   0x0 /* no retention for any SRAM-bank */
 
#define MCUCFG_SRAM_RET_B0   0x1
 
#define MCUCFG_SRAM_RET_B01   0x3
 
#define MCUCFG_SRAM_RET_B012   0x7
 
#define MCUCFG_SRAM_RET_B0124   0xF /* retention for banks 0, 1, 2, and 3 */
 
#define MCUCFG_SRAM_FIXED_WU_EN   0x100
 
#define MCUCFG_SRAM_VIRT_OFF   0x200
 
#define AUXCFG_RAM_RET_EN   0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */
 
#define AUXCTL_AUX_FORCE_ON   0x1
 
#define AUXCTL_SWEV   0x2
 
#define AUXCTL_SCE_RUN_EN   0x3
 
#define AUXCTL_RESET_REQ   0x80000000
 
#define PWRSTAT_AUX_RESET_DONE   0x2
 
#define PWRSTAT_AUX_BUS_CONNECTED   0x4
 
#define PWRSTAT_MCU_PD_ON   0x10
 
#define PWRSTAT_AUX_PD_ON   0x20
 
#define PWRSTAT_JTAG_PD_ON   0x40
 
#define PWRSTAT_AUX_PWR_DNW   0x200
 
#define SHUTDOWN_EN   0x1 /* register/cancel shutdown request */
 
#define AONWUC_CTL0_MCU_SRAM_ERASE   0x4
 
#define AONWUC_CTL0_AUX_SRAM_ERASE   0x8
 
#define AONWUC_CTL0_PWR_DWN_DIS   0x10 /* disable powerdown on request */
 
#define AONWUC_CTL1_MCU_WARM_RESET   0x1 /* last MCU reset was a warm reset */
 
#define AONWUC_CTL1_MCU_RESET_SRC   0x2 /* JTAG was source of last reset (MCU SW elsewise) */
 
#define RECHARGECFG_PER_E_mask   0x00000007 /* number of 32KHz clocks between activation of recharge controller: */
 
#define RECHARGECFG_PER_M_mask   0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
 
#define RECHARGECFG_MAX_PER_E_mask   0x00000700 /* maximum period the recharge algorithm can take */
 
#define RECHARGECFG_MAX_PER_M_mask   0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */
 
#define RECHARGECFG_C1_mask   0x000F0000 /* i resign */
 
#define RECHARGECFG_C2_mask   0x000F0000
 
#define RECHARGECFG_ADAPTIVE_EN   0x80000000
 
#define RECHARGESTAT_MAX_USED_PER_mask   0x0FFFF
 
#define RECHARGESTAT_VDDR_SMPLS_mask   0xF0000
 
#define OSCCFG_PER_E_mask   0x07 /* number of 32KHz clocks between oscillator amplitude callibrations */
 
#define OSCCFG_PER_M_mask   0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
 
#define JTAGCFG_JTAG_PD_FORCE_ON   0x10
 
#define AON_WUC_BASE   0x40091000
 AON_WUC base address.
 
#define AON_RTC_BASE   (PERIPH_BASE + 0x92000)
 AON_RTC base address.
 
#define AON_WUC   ((aon_wuc_regs_t *) (AON_WUC_BASE))
 AON_WUC register bank.
 
#define AON_RTC_CTL_RTC_UPD_EN   0x00000002
 RTC_UPD is a 16 KHz signal used to sync up the radio timer. More...
 
#define PRCM_BASE   (PERIPH_BASE + 0x82000)
 PRCM base address.
 
#define PRCM_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x82000)
 PRCM base address (nonbuf)
 
#define PRCM   ((prcm_regs_t *) (PRCM_BASE))
 PRCM register bank.
 
#define PRCM_NONBUF   ((prcm_regs_t *) (PRCM_BASE_NONBUF))
 PRCM register bank (nonbuf)
 
#define AUX_AIODIO0_BASE   (PERIPH_BASE + 0xCC000)
 AUX_AIODIO0 base address.
 
#define AUX_AIODIO1_BASE   (PERIPH_BASE + 0xCD000)
 AUX_AIODIO1 base address.
 
#define AUX_AIODIO2_BASE   (PERIPH_BASE + 0xCE000)
 AUX_AIODIO2 base address.
 
#define AUX_AIODIO3_BASE   (PERIPH_BASE + 0xCF000)
 AUX_AIODIO3 base address.
 
#define AUX_TDC_BASE   (PERIPH_BASE + 0xC4000)
 AUX_TDC base address.
 
#define AUX_EVCTL_BASE   (PERIPH_BASE + 0xC5000)
 AUX_EVCTL base address.
 
#define AUX_SYSIF_BASE   (PERIPH_BASE + 0xC6000)
 AUX_SYSIF base address.
 
#define AUX_TIMER01_BASE   (PERIPH_BASE + 0xC7000)
 AUX_TIMER01 base address.
 
#define AUX_TIMER2_BASE   (PERIPH_BASE + 0xC3000)
 AUX_TIMER2 base address.
 
#define AUX_SMPH_BASE   (PERIPH_BASE + 0xC8000)
 AUX_SMPH base address.
 
#define AUX_ANAIF_BASE   (PERIPH_BASE + 0xC9000)
 AUX_ANAIF base address.
 
#define ADI_4_AUX_BASE   (PERIPH_BASE + 0xCB000)
 ADI_4_AUX base address.
 
#define ADI_4_AUX_BASE_M8   (ADI_4_AUX_BASE + ADI_MASK8B)
 ADI_4_AUX base address for masked 8-bit access.
 
#define FCFG_BASE   (0x50001000)
 FCFG1 base address.
 
#define AON_PMCTL_BASE   (PERIPH_BASE + 0x90000)
 AON_PMCTL base address.
 
#define AON_RTC_BASE   (PERIPH_BASE + 0x92000)
 AON_RTC base address.
 
#define PRCM_BASE   (PERIPH_BASE + 0x82000)
 PRCM base address.
 
#define PRCM_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x82000)
 PRCM base address (nonbuf)
 
#define PRCM   ((prcm_regs_t *) (PRCM_BASE))
 PRCM register bank.
 
#define PRCM_NONBUF   ((prcm_regs_t *) (PRCM_BASE_NONBUF))
 PRCM register bank (nonbuf)
 
#define FLASH_BASE   0x00000000
 CMSIS includes. More...
 
#define ADI_3_REFSYS_BASE   (PERIPH_BASE + 0x86200)
 ADI3 base address.
 
#define ADI_3_REFSYS_BASE_SET   (ADI_3_REFSYS_BASE + ADI_SET)
 ADI3 base address for SET instruction.
 
#define ADI_3_REFSYS_BASE_CLR   (ADI_3_REFSYS_BASE + ADI_CLR)
 ADI3 base address for CLR instruction.
 
#define ADI_3_REFSYS_BASE_M4   (ADI_3_REFSYS_BASE + ADI_MASK4B)
 ADI3 base address for 4-bit masked access.
 
#define CCFG_BASE   (0x50003000)
 CCFG base address.
 
#define GPIO_BASE   (0x40022000)
 GPIO base address.
 
#define I2C_BASE   (PERIPH_BASE + 0x2000)
 I2C base address.
 
#define MCU_IOC_BASE   (0x40081000)
 IOC (MCU) base address.
 
#define AON_IOC_BASE   (PERIPH_BASE + 0x94000)
 AON_IOC base address.
 
#define RFC_DBELL_BASE   (PERIPH_BASE + 0x41000)
 RFC_DBELL base address.
 
#define RFC_DBELL_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x41000)
 RFC_DBELL base address.
 
#define RFC_PWR_BASE   (PERIPH_BASE + 0x40000)
 RFC_PWR base address.
 
#define RFC_PWR_BASE_NONBUF   (PERIPH_BASE_NONBUF + 0x40000)
 RFC_PWR base address.
 
#define UART0_BASE   (PERIPH_BASE + 0x1000)
 UART0 base address.
 
#define UART1_BASE   (PERIPH_BASE + 0xB000)
 UART1 base address.
 
#define FLASH_BASEADDR   (PERIPH_BASE + 0x30000)
 FLASH base address.
 
#define VIMS_BASE   (PERIPH_BASE + 0x34000)
 VIMS base address.
 
#define FLASH   ((flash_regs_t *) (FLASH_BASEADDR))
 FLASH register bank.
 
#define VIMS   ((vims_regs_t *) (VIMS_BASE))
 VIMS register bank.
 
#define VIMS_CTL_STATS_CLR   0x80000000
 VIMS register values.
 
#define VIMS_CTL_STATS_CLR_m   0x80000000
 
#define VIMS_CTL_STATS_EN   0x40000000
 
#define VIMS_CTL_STATS_EN_m   0x40000000
 
#define VIMS_CTL_DYN_CG_EN   0x20000000
 
#define VIMS_CTL_DYN_CG_EN_m   0x20000000
 
#define VIMS_CTL_IDCODE_LB_DIS   0x00000020
 
#define VIMS_CTL_IDCODE_LB_DIS_m   0x00000020
 
#define VIMS_CTL_SYSBUS_LB_DIS   0x00000010
 
#define VIMS_CTL_SYSBUS_LB_DIS_m   0x00000010
 
#define VIMS_CTL_ARB_CFG   0x00000008
 
#define VIMS_CTL_ARB_CFG_m   0x00000008
 
#define VIMS_CTL_PREF_EN   0x00000004
 
#define VIMS_CTL_PREF_EN_m   0x00000004
 
#define VIMS_CTL_MODE_GPRAM   0x00000000
 
#define VIMS_CTL_MODE_CACHE   0x00000001
 
#define VIMS_CTL_MODE_SPLIT   0x00000002
 
#define VIMS_CTL_MODE_OFF   0x00000003
 
#define VIMS_CTL_MODE_m   0x00000003
 
#define VIMS_STAT_MODE_CHANGING   0x00000008
 
#define WDT_BASE   0x40080000
 WDT base address.
 
#define WDT   ((wdt_regs_t *) (WDT_BASE))
 WDT register bank.
 

Macro Definition Documentation

◆ AON_RTC_CTL_RTC_UPD_EN

#define AON_RTC_CTL_RTC_UPD_EN   0x00000002

RTC_UPD is a 16 KHz signal used to sync up the radio timer.

The 16 Khz is SCLK_LF divided by 2

0h = RTC_UPD signal is forced to 0 1h = RTC_UPD signal is toggling @16 kHz

Definition at line 219 of file cc26x0_prcm.h.

◆ FLASH_BASE

#define FLASH_BASE   0x00000000

CMSIS includes.

FLASH base address

Definition at line 144 of file cc26xx_cc13xx.h.