RIOT/html/cc26x2__cc13x2__aux_8h_source.html

/*

 * Copyright (C) 2016 Leon George

 * Copyright (C) 2018 Anton Gerasimov

 *

 * This file is subject to the terms and conditions of the GNU Lesser General

 * Public License v2.1. See the file LICENSE in the top level directory for more

 * details.

 */

#ifndef CC26X2_CC13X2_AUX_H

#define CC26X2_CC13X2_AUX_H


#include <stdbool.h>


#include "cc26xx_cc13xx.h"


#ifdef __cplusplus

extern "C" {

#endif


typedef struct {

    reg32_t IOMODE;

    reg32_t GPIODIE;

    reg32_t IOPOE;

    reg32_t GPIODOUT;

    reg32_t GPIODIN;

    reg32_t GPIODOUTSET;

    reg32_t GPIODOUTCLR;

    reg32_t GPIODOUTTGL;

    reg32_t IO0PSEL;

    reg32_t IO1PSEL;

    reg32_t IO2PSEL;

    reg32_t IO3PSEL;

    reg32_t IO4PSEL;

    reg32_t IO5PSEL;

    reg32_t IO6PSEL;

    reg32_t IO7PSEL;

    reg32_t IOMODEH;

    reg32_t IOMODEL;

} aux_aiodio_regs_t;


#define AUX_AIODIO0_BASE     (PERIPH_BASE + 0xCC000)


#define AUX_AIODIO1_BASE     (PERIPH_BASE + 0xCD000)


#define AUX_AIODIO2_BASE     (PERIPH_BASE + 0xCE000)


#define AUX_AIODIO3_BASE     (PERIPH_BASE + 0xCF000)


#define AUX_AIODIO0          ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE))


#define AUX_AIODIO1          ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE))


#define AUX_AIODIO2          ((aux_aiodio_regs_t *) (AUX_AIODIO2_BASE))


#define AUX_AIODIO3          ((aux_aiodio_regs_t *) (AUX_AIODIO3_BASE))


typedef struct {

    reg32_t CTL;

    reg32_t STAT;

    reg32_t RESULT;

    reg32_t SATCFG;

    reg32_t TRIGSRC;

    reg32_t TRIGCNT;

    reg32_t TRIGCNTLOAD;

    reg32_t TRIGCNTCFG;

    reg32_t PRECTL;

    reg32_t PRECNTR;

} aux_tdc_regs_t;


#define AUX_TDC_BASE         (PERIPH_BASE + 0xC4000)


#define AUX_TDC              ((aux_tdc_regs_t *) (AUX_TDC_BASE))


typedef struct {

    reg32_t EVSTAT0;

    reg32_t EVSTAT1;

    reg32_t EVSTAT2;

    reg32_t EVSTAT3;

    reg32_t SCEWEVCFG0;

    reg32_t SCEWEVCFG1;

    reg32_t DMACTL;

    reg32_t __reserved1;

    reg32_t SWEVSET;

    reg32_t EVTOAONFLAGS;

    reg32_t EVTOAONPOL;

    reg32_t EVTOAONFLAGSCLR;

    reg32_t EVTOMCUFLAGS;

    reg32_t EVTOMCUPOL;

    reg32_t EVTOMCUFLAGSCLR;

    reg32_t COMBEVTOMCUMASK;

    reg32_t EVOBSCFG;

    reg32_t PROGDLY;

    reg32_t MANUAL;

    reg32_t EVSTAT0L;

    reg32_t EVSTAT0H;

    reg32_t EVSTAT1L;

    reg32_t EVSTAT1H;

    reg32_t EVSTAT2L;

    reg32_t EVSTAT2H;

    reg32_t EVSTAT3L;

    reg32_t EVSTAT3H;

} aux_evctl_regs_t;


#define AUX_EVCTL_BASE       (PERIPH_BASE + 0xC5000)


#define AUX_EVCTL            ((aux_evctl_regs_t *) (AUX_EVCTL_BASE))


typedef struct {

    reg32_t OPMODEREQ;

    reg32_t OPMODEACK;

    reg32_t PROGWU0CFG;

    reg32_t PROGWU1CFG;

    reg32_t PROGWU2CFG;

    reg32_t PROGWU3CFG;

    reg32_t SWWUTRIG;

    reg32_t WUFLAGS;

    reg32_t WUFLAGSCLR;

    reg32_t WUGATE;

    reg32_t VECCFG0;

    reg32_t VECCFG1;

    reg32_t VECCFG2;

    reg32_t VECCFG3;

    reg32_t VECCFG4;

    reg32_t VECCFG5;

    reg32_t VECCFG6;

    reg32_t VECCFG7;

    reg32_t EVSYNCRATE;

    reg32_t PEROPRATE;

    reg32_t ADCCLKCTL;

    reg32_t TDCCLKCTL;

    reg32_t TDCREFCLKCTL;

    reg32_t TIMER2CLKCTL;

    reg32_t TIMER2CLKSTAT;

    reg32_t TIMER2CLKSWITCH;

    reg32_t TIMER2DBGCTL;

    reg32_t __reserved1;

    reg32_t CLKSHIFTDET;

    reg32_t RECHARGETRIG;

    reg32_t RECHARGEDET;

    reg32_t RTCSUBSECINC0;

    reg32_t RTCSUBSECINC1;

    reg32_t RTCSUBSECINCCTL;

    reg32_t RTCSEC;

    reg32_t RTCSUBSEC;

    reg32_t RTCEVCLR;

    reg32_t BATMONBAT;

    reg32_t __reserved2;

    reg32_t BATMONTEMP;

    reg32_t TIMERHALT;

    reg32_t __reserved3[0x3];

    reg32_t TIMER2BRIDGE;

    reg32_t SWPWRPROF;

} aux_sysif_regs_t;


#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003

#define AUX_SYSIF_OPMODEREQ_REQ_PDA  0x00000002

#define AUX_SYSIF_OPMODEREQ_REQ_LP   0x00000001

#define AUX_SYSIF_OPMODEREQ_REQ_A    0x00000000


#define AUX_SYSIF_BASE       (PERIPH_BASE + 0xC6000)


#define AUX_SYSIF            ((aux_sysif_regs_t *) (AUX_SYSIF_BASE))


void aux_sysif_opmode_change(uint32_t target_opmode);

typedef struct {

    reg32_t T0CFG;

    reg32_t T0CTL;

    reg32_t T0TARGET;

    reg32_t T0CNTR;

    reg32_t T1CFG;

    reg32_t T1TARGET;

    reg32_t T1CTL;

    reg32_t T1CNTR;

} aux_timer01_regs_t;


#define AUX_TIMER01_BASE     (PERIPH_BASE + 0xC7000)


#define AUX_TIMER01          ((aux_timer01_regs_t *) (AUX_TIMER01_BASE))


typedef struct {

    reg32_t CTL;

    reg32_t TARGET;

    reg32_t SHDWTARGET;

    reg32_t CNTR;

    reg32_t PRECFG;

    reg32_t EVCTL;

    reg32_t PULSETRIG;

    reg32_t __reserved1[0x19];

    reg32_t CH0EVCFG;

    reg32_t CH0CCFG;

    reg32_t CH0PCC;

    reg32_t CH0CC;

    reg32_t CH1EVCFG;

    reg32_t CH1CCFG;

    reg32_t CH1PCC;

    reg32_t CH1CC;

    reg32_t CH2EVCFG;

    reg32_t CH2CCFG;

    reg32_t CH2PCC;

    reg32_t CH2CC;

    reg32_t CH3EVCFG;

    reg32_t CH3CCFG;

    reg32_t CH3PCC;

    reg32_t CH3CC;

} aux_timer2_regs_t;


#define AUX_TIMER2_BASE      (PERIPH_BASE + 0xC3000)


#define AUX_TIMER2           ((aux_timer2_regs_t *) (AUX_TIMER2_BASE))


typedef struct {

    reg32_t SMPH0;

    reg32_t SMPH1;

    reg32_t SMPH2;

    reg32_t SMPH3;

    reg32_t SMPH4;

    reg32_t SMPH5;

    reg32_t SMPH6;

    reg32_t SMPH7;

    reg32_t AUTOTAKE;

} aux_smph_regs_t;


#define AUX_SMPH_BASE        (PERIPH_BASE + 0xC8000)


#define AUX_SMPH             ((aux_smph_regs_t *) (AUX_SMPH_BASE))


typedef struct {

    reg32_t __reserved1[0x4];

    reg32_t ADCCTL;

    reg32_t ADCFIFOSTAT;

    reg32_t ADCFIFO;

    reg32_t ADCTRIG;

    reg32_t ISRCCTL;

    reg32_t __reserved2[0x3];

    reg32_t DACCTL;

    reg32_t LPMBIASCTL;

    reg32_t DACSMPLCTL;

    reg32_t DACSMPLCFG0;

    reg32_t DACSMPLCFG1;

    reg32_t DACVALUE;

    reg32_t DACSTAT;

} aux_anaif_regs_t;


#define AUX_ANAIF_BASE       (PERIPH_BASE + 0xC9000)


#define AUX_ANAIF            ((aux_anaif_regs_t *) (AUX_ANAIF_BASE))


typedef struct {

    reg8_t MUX0;

    reg8_t MUX1;

    reg8_t MUX2;

    reg8_t MUX3;

    reg8_t ISRC;

    reg8_t COMP;

    reg8_t MUX4;

    reg8_t ADC0;

    reg8_t ADC1;

    reg8_t ADCREF0;

    reg8_t ADCREF1;

    reg8_t __reserved1[0x3];

    reg8_t LPMBIAS;

} adi_4_aux_regs_t;


typedef struct {

    reg8_m8_t MUX0;

    reg8_m8_t MUX1;

    reg8_m8_t MUX2;

    reg8_m8_t MUX3;

    reg8_m8_t ISRC;

    reg8_m8_t COMP;

    reg8_m8_t MUX4;

    reg8_m8_t ADC0;

    reg8_m8_t ADC1;

    reg8_m8_t ADCREF0;

    reg8_m8_t ADCREF1;

    reg8_m8_t __reserved1[0x3];

    reg8_m8_t LPMBIAS;

} adi_4_aux_regs_m8_t;


#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_m 0x00000038

#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_s 3

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_m    0x0000003F

#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_s    0


#define ADI_4_AUX_BASE       (PERIPH_BASE + 0xCB000)


#define ADI_4_AUX_BASE_M8    (ADI_4_AUX_BASE + ADI_MASK8B)


#define ADI_4_AUX            ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE))


#define ADI_4_AUX_M8         ((adi_4_aux_regs_m8_t *) (ADI_4_AUX_BASE_M8))


#define ADDI_SEM             AUX_SMPH->SMPH0


#ifdef __cplusplus

} /* end extern "C" */

#endif


#endif /* CC26X2_CC13X2_AUX_H */