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25 #include <stdatomic.h>
38 #define DPL_ENTER_CRITICAL(_sr) (_sr = dpl_hw_enter_critical())
39 #define DPL_EXIT_CRITICAL(_sr) (dpl_hw_exit_critical(_sr))
40 #define DPL_ASSERT_CRITICAL() assert(dpl_hw_is_in_critical())
static uint32_t dpl_hw_enter_critical(void)
Disable ISRs.
MAYBE_INLINE unsigned irq_disable(void)
This function sets the IRQ disable bit in the status register.
static void dpl_hw_exit_critical(uint32_t ctx)
Restores ISR context.
POSIX.1-2008 compliant version of the assert macro.
MAYBE_INLINE void irq_restore(unsigned state)
This function restores the IRQ disable bit in the status register to the value contained within passe...
Type with the same alignment and size as atomic_uint
atomic_uint dpl_in_critical
variable to check if ISR are disabled
static bool dpl_hw_is_in_critical(void)
Check if is in critical section.
uwb-core DPL (Decawave Porting Layer) types
uint32_t dpl_sr_t
CPU status register.