Go to the documentation of this file.
43 #define GPIO_UNDEF (0xffff)
49 #define GPIO_PIN(x, y) ((gpio_t)(((x & 0xff) << 8) | (1 << (y & 0x07))))
54 #define SPI_HWCS(x) (SPI_CS_UNDEF)
61 #define HAVE_GPIO_FLANK_T
72 #define HAVE_SPI_MODE_T
77 SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH),
84 SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH),
93 #define HAVE_SPI_CLK_T
128 #define PERIPH_SPI_NEEDS_INIT_CS
129 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
130 #define PERIPH_SPI_NEEDS_TRANSFER_REG
131 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
@ SPI_MODE_3
CPOL=1, CPHA=1.
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
@ SPI_MODE_0
CPOL=0, CPHA=0.
Cortex CMSIS style definition of MSP430 registers.
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
@ GPIO_FALLING
emit interrupt on falling flank
@ GPIO_RISING
emit interrupt on rising flank
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
uint32_t spi_clk_t
SPI clock type.
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
void gpio_periph_mode(gpio_t pin, bool enable)
Enable or disable a pin to be used by peripheral modules.
@ GPIO_BOTH
emit interrupt on both flanks
unsigned int gpio_t
GPIO type identifier.
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
@ SPI_MODE_1
CPOL=0, CPHA=1.
@ SPI_MODE_2
CPOL=1, CPHA=0.