periph_conf.h
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1 /*
2  * Copyright (C) 2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* This board provides an LSE */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 /* This board provides an HSE */
28 #ifndef CONFIG_BOARD_HAS_HSE
29 #define CONFIG_BOARD_HAS_HSE 1
30 #endif
31 
32 /* The HSE provides a 25MHz clock */
33 #define CLOCK_HSE MHZ(25)
34 
35 #include "periph_cpu.h"
36 #include "f2f4f7/cfg_clock_default_216.h"
37 #include "cfg_rtt_default.h"
38 #include "cfg_timer_tim2.h"
39 #include "cfg_usb_otg_fs.h"
40 
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44 
49 static const uart_conf_t uart_config[] = {
50  {
51  .dev = USART1,
52  .rcc_mask = RCC_APB2ENR_USART1EN,
53  .rx_pin = GPIO_PIN(PORT_A, 10),
54  .tx_pin = GPIO_PIN(PORT_A, 9),
55  .rx_af = GPIO_AF7,
56  .tx_af = GPIO_AF7,
57  .bus = APB2,
58  .irqn = USART1_IRQn,
59 #ifdef UART_USE_DMA
60  .dma_stream = 4,
61  .dma_chan = 4
62 #endif
63  }
64 };
65 
66 #define UART_0_ISR (isr_usart1)
67 #define UART_0_DMA_ISR (isr_dma1_stream4)
68 
69 #define UART_NUMOF ARRAY_SIZE(uart_config)
70 
72 #ifdef __cplusplus
73 }
74 #endif
75 
76 #endif /* PERIPH_CONF_H */
77 
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
cfg_usb_otg_fs.h
Common configuration for STM32 OTG FS peripheral.
cfg_clock_default_216.h
Default STM32F7 clock configuration for 216MHz boards.
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
cfg_timer_tim2.h
Common configuration for STM32 Timer peripheral based on TIM2.