cc26xx_cc13xx_i2c.h
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1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CC26XX_CC13XX_I2C_H
20 #define CC26XX_CC13XX_I2C_H
21 
22 #include "cc26xx_cc13xx.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 
32 typedef struct {
33  reg32_t SOAR;
34  union {
35  reg32_t SSTAT;
36  reg32_t SCTL;
37  };
38  reg32_t SDR;
39  reg32_t SIMR;
40  reg32_t SRIS;
41  reg32_t SMIS;
42  reg32_t SICR;
43  reg32_t __reserved[0x1F9];
44  reg32_t MSA;
45  union {
46  reg32_t MSTAT;
47  reg32_t MCTRL;
48  };
49  reg32_t MDR;
50  reg32_t MTPR;
51  reg32_t MIMR;
52  reg32_t MRIS;
53  reg32_t MMIS;
54  reg32_t MICR;
55  reg32_t MCR;
56 } i2c_regs_t;
57 
63 #define MCR_MFE 0x00000010
64 
78 #define MTPR_TPR_100KHZ 0x00000017
79 
87 #define MSA_RS 0x00000001
88 
96 #define MSTAT_BUSBSY 0x00000040
97 
103 #define MSTAT_IDLE 0x00000020
104 
105 
111 #define MSTAT_ARBLST 0x00000010
112 
118 #define MSTAT_DATACK_N 0x00000008
119 
125 #define MSTAT_ADRACK_N 0x00000004
126 
132 #define MSTAT_ERR 0x00000002
133 
147 #define MSTAT_BUSY 0x00000001
148 
160 #define MCTRL_ACK 0x00000008
161 
170 #define MCTRL_STOP 0x00000004
171 
179 #define MCTRL_START 0x00000002
180 
188 #define MCTRL_RUN 0x00000001
189 
193 #define I2C_BASE (PERIPH_BASE + 0x2000)
196 #define I2C ((i2c_regs_t *) (I2C_BASE))
198 #ifdef __cplusplus
199 }
200 #endif
201 
202 #endif /* CC26XX_CC13XX_I2C_H */
203 
i2c_regs_t::MIMR
reg32_t MIMR
master interrupt mask
Definition: cc26xx_cc13xx_i2c.h:51
i2c_regs_t::SIMR
reg32_t SIMR
slave interrupt mask
Definition: cc26xx_cc13xx_i2c.h:39
i2c_regs_t::SCTL
reg32_t SCTL
slave control
Definition: cc26xx_cc13xx_i2c.h:36
i2c_regs_t
I2C registers.
Definition: cc26xx_cc13xx_i2c.h:32
i2c_regs_t::MTPR
reg32_t MTPR
master timer period
Definition: cc26xx_cc13xx_i2c.h:50
i2c_regs_t::SRIS
reg32_t SRIS
slave raw interrupt status
Definition: cc26xx_cc13xx_i2c.h:40
i2c_regs_t::SICR
reg32_t SICR
slave interrupt clear
Definition: cc26xx_cc13xx_i2c.h:42
i2c_regs_t::SDR
reg32_t SDR
slave data
Definition: cc26xx_cc13xx_i2c.h:38
i2c_regs_t::MSTAT
reg32_t MSTAT
master status
Definition: cc26xx_cc13xx_i2c.h:46
i2c_regs_t::MCTRL
reg32_t MCTRL
master control
Definition: cc26xx_cc13xx_i2c.h:47
i2c_regs_t::SOAR
reg32_t SOAR
slave own address
Definition: cc26xx_cc13xx_i2c.h:33
cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
i2c_regs_t::SSTAT
reg32_t SSTAT
slave status
Definition: cc26xx_cc13xx_i2c.h:35
i2c_regs_t::MMIS
reg32_t MMIS
master masked interrupt statues
Definition: cc26xx_cc13xx_i2c.h:53
i2c_regs_t::MSA
reg32_t MSA
master slave address
Definition: cc26xx_cc13xx_i2c.h:44
i2c_regs_t::MICR
reg32_t MICR
master interrupt clear
Definition: cc26xx_cc13xx_i2c.h:54
i2c_regs_t::MCR
reg32_t MCR
master configuration
Definition: cc26xx_cc13xx_i2c.h:55
i2c_regs_t::MDR
reg32_t MDR
master data
Definition: cc26xx_cc13xx_i2c.h:49
i2c_regs_t::SMIS
reg32_t SMIS
slave masked interrupt status
Definition: cc26xx_cc13xx_i2c.h:41
i2c_regs_t::MRIS
reg32_t MRIS
master raw interrupt status
Definition: cc26xx_cc13xx_i2c.h:52