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cc26xx_cc13xx_i2c.h
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/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CC26XX_CC13XX_I2C_H
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#define CC26XX_CC13XX_I2C_H
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#include "
cc26xx_cc13xx.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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reg32_t
SOAR
;
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union
{
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reg32_t
SSTAT
;
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reg32_t
SCTL
;
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};
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reg32_t
SDR
;
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reg32_t
SIMR
;
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reg32_t
SRIS
;
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reg32_t
SMIS
;
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reg32_t
SICR
;
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reg32_t __reserved[0x1F9];
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reg32_t
MSA
;
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union
{
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reg32_t
MSTAT
;
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reg32_t
MCTRL
;
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};
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reg32_t
MDR
;
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reg32_t
MTPR
;
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reg32_t
MIMR
;
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reg32_t
MRIS
;
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reg32_t
MMIS
;
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reg32_t
MICR
;
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reg32_t
MCR
;
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}
i2c_regs_t
;
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#define MCR_MFE 0x00000010
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#define MTPR_TPR_100KHZ 0x00000017
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#define MSA_RS 0x00000001
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#define MSTAT_BUSBSY 0x00000040
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#define MSTAT_IDLE 0x00000020
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#define MSTAT_ARBLST 0x00000010
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#define MSTAT_DATACK_N 0x00000008
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#define MSTAT_ADRACK_N 0x00000004
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#define MSTAT_ERR 0x00000002
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#define MSTAT_BUSY 0x00000001
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#define MCTRL_ACK 0x00000008
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#define MCTRL_STOP 0x00000004
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#define MCTRL_START 0x00000002
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#define MCTRL_RUN 0x00000001
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#define I2C_BASE (PERIPH_BASE + 0x2000)
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#define I2C ((i2c_regs_t *) (I2C_BASE))
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#ifdef __cplusplus
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}
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#endif
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#endif
/* CC26XX_CC13XX_I2C_H */
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i2c_regs_t::MIMR
reg32_t MIMR
master interrupt mask
Definition:
cc26xx_cc13xx_i2c.h:51
i2c_regs_t::SIMR
reg32_t SIMR
slave interrupt mask
Definition:
cc26xx_cc13xx_i2c.h:39
i2c_regs_t::SCTL
reg32_t SCTL
slave control
Definition:
cc26xx_cc13xx_i2c.h:36
i2c_regs_t
I2C registers.
Definition:
cc26xx_cc13xx_i2c.h:32
i2c_regs_t::MTPR
reg32_t MTPR
master timer period
Definition:
cc26xx_cc13xx_i2c.h:50
i2c_regs_t::SRIS
reg32_t SRIS
slave raw interrupt status
Definition:
cc26xx_cc13xx_i2c.h:40
i2c_regs_t::SICR
reg32_t SICR
slave interrupt clear
Definition:
cc26xx_cc13xx_i2c.h:42
i2c_regs_t::SDR
reg32_t SDR
slave data
Definition:
cc26xx_cc13xx_i2c.h:38
i2c_regs_t::MSTAT
reg32_t MSTAT
master status
Definition:
cc26xx_cc13xx_i2c.h:46
i2c_regs_t::MCTRL
reg32_t MCTRL
master control
Definition:
cc26xx_cc13xx_i2c.h:47
i2c_regs_t::SOAR
reg32_t SOAR
slave own address
Definition:
cc26xx_cc13xx_i2c.h:33
cc26xx_cc13xx.h
CC26xx, CC13xx definitions.
i2c_regs_t::SSTAT
reg32_t SSTAT
slave status
Definition:
cc26xx_cc13xx_i2c.h:35
i2c_regs_t::MMIS
reg32_t MMIS
master masked interrupt statues
Definition:
cc26xx_cc13xx_i2c.h:53
i2c_regs_t::MSA
reg32_t MSA
master slave address
Definition:
cc26xx_cc13xx_i2c.h:44
i2c_regs_t::MICR
reg32_t MICR
master interrupt clear
Definition:
cc26xx_cc13xx_i2c.h:54
i2c_regs_t::MCR
reg32_t MCR
master configuration
Definition:
cc26xx_cc13xx_i2c.h:55
i2c_regs_t::MDR
reg32_t MDR
master data
Definition:
cc26xx_cc13xx_i2c.h:49
i2c_regs_t::SMIS
reg32_t SMIS
slave masked interrupt status
Definition:
cc26xx_cc13xx_i2c.h:41
i2c_regs_t::MRIS
reg32_t MRIS
master raw interrupt status
Definition:
cc26xx_cc13xx_i2c.h:52
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