cfg_i2c1_pb6_pb7.h
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1 /*
2  * Copyright (C) 2019 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CFG_I2C1_PB6_PB7_H
20 #define CFG_I2C1_PB6_PB7_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 static const i2c_conf_t i2c_config[] = {
33  {
34  .dev = I2C1,
35  .speed = I2C_SPEED_NORMAL,
36  .scl_pin = GPIO_PIN(PORT_B, 6),
37  .sda_pin = GPIO_PIN(PORT_B, 7),
38 #if CPU_FAM_STM32L4
39  .scl_af = GPIO_AF4,
40  .sda_af = GPIO_AF4,
41 #else /* CPU_FAM_STM32L0 */
42  .scl_af = GPIO_AF1,
43  .sda_af = GPIO_AF1,
44 #endif
45  .bus = APB1,
46 #if CPU_FAM_STM32L4
47  .rcc_mask = RCC_APB1ENR1_I2C1EN,
48  .irqn = I2C1_ER_IRQn,
49 #else /* CPU_FAM_STM32L0 */
50  .rcc_mask = RCC_APB1ENR_I2C1EN,
51  .irqn = I2C1_IRQn
52 #endif
53  }
54 };
55 
56 #if CPU_FAM_STM32L4
57 #define I2C_0_ISR isr_i2c1_er
58 #else /* CPU_FAM_STM32L0 */
59 #define I2C_0_ISR isr_i2c1
60 #endif
61 
62 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
63 
64 #ifdef __cplusplus
65 }
66 #endif
67 
68 #endif /* CFG_I2C1_PB6_PB7_H */
69 
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: periph_cpu_common.h:90
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
GPIO_AF1
@ GPIO_AF1
use alternate function 1
Definition: periph_cpu_common.h:87
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
i2c_conf_t::dev
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:247
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176