periph_cpu.h
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1 /*
2  * Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com>
3  * Copyright (C) 2017 Marc Poulhiès <dkm@kataplop.net>
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define HAVE_GPIO_T
35 typedef uint32_t gpio_t;
36 #define GPIO_PIN(x, y) ((gpio_t)((x<<4) | y))
37 
39 #ifndef DOXYGEN
40 
44 #define HAVE_GPIO_MODE_T
45 typedef enum {
46  GPIO_IN = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD << 4)),
47  GPIO_IN_PD = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPD << 4)),
48  GPIO_IN_PU = (GPIO_DIR_MODE_IN | (GPIO_PIN_TYPE_STD_WPU << 4)),
49  GPIO_OUT = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_STD << 4)),
50  GPIO_OD = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD << 4)),
51  GPIO_OD_PU = (GPIO_DIR_MODE_OUT | (GPIO_PIN_TYPE_OD_WPU << 4)),
52 } gpio_mode_t;
54 #endif /* ndef DOXYGEN */
55 
60 #define HAVE_GPIO_DIR_T
61 typedef enum {
62  GPIO_DIR_IN = GPIO_DIR_MODE_IN,
63  GPIO_DIR_OUT = GPIO_DIR_MODE_OUT
64 } gpio_dir_t;
67 #ifndef DOXYGEN
68 
72 #define HAVE_GPIO_FLANK_T
73 typedef enum {
74  GPIO_FALLING = GPIO_FALLING_EDGE,
75  GPIO_RISING = GPIO_RISING_EDGE,
76  GPIO_BOTH = GPIO_BOTH_EDGES
77 } gpio_flank_t;
79 #endif /* ndef DOXYGEN */
80 
84 enum {
85  PORT_A = 0,
86  PORT_B = 1,
87  PORT_C = 2,
88  PORT_D = 3,
89  PORT_E = 4,
90  PORT_F = 5,
91 };
92 
96 #ifndef DOXYGEN
97 #define HAVE_ADC_RES_T
98 typedef enum {
99  ADC_RES_6BIT = 0xa00,
100  ADC_RES_8BIT = 0xb00,
101  ADC_RES_10BIT = ADC_RES_10BIT_S,
102  ADC_RES_12BIT = ADC_RES_12BIT_S,
103  ADC_RES_14BIT = 0xc00,
104  ADC_RES_16BIT = 0xd00,
105 } adc_res_t;
106 #endif /* ndef DOXYGEN */
107 
111 typedef struct {
112  uint32_t dev;
113  uint32_t max;
114  int irqn;
115  uint32_t sysctl;
116  uint32_t intbase;
117  int channels;
118 } timer_conf_t;
119 
125 #define SPI_HWCS(x) (UINT_MAX - 1)
126 
131 typedef struct {
132  unsigned long ssi_sysctl;
133  unsigned long ssi_base;
134  unsigned long gpio_sysctl;
135  unsigned long gpio_port;
136  struct {
137  unsigned long clk;
138  unsigned long fss;
139  unsigned long rx;
140  unsigned long tx;
141  unsigned long mask;
142  } pins;
143 } spi_conf_t;
150 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
151 #define PERIPH_SPI_NEEDS_TRANSFER_REG 1
152 #define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
153 #define PERIPH_SPI_NEEDS_INIT_CS 1
154 
156 #ifndef DOXYGEN
157 
161 #define HAVE_SPI_CLK_T 1
162 typedef enum {
163  SPI_CLK_100KHZ = 100000,
164  SPI_CLK_400KHZ = 400000,
165  SPI_CLK_1MHZ = 1000000,
166  SPI_CLK_4MHZ = 4000000,
167  SPI_CLK_5MHZ = 5000000,
168  SPI_CLK_10MHZ = 10000000,
169 } spi_clk_t;
176 #define HAVE_SPI_MODE_T 1
177 typedef enum {
178  SPI_MODE_0 = SSI_FRF_MOTO_MODE_0,
179  SPI_MODE_1 = SSI_FRF_MOTO_MODE_1,
180  SPI_MODE_2 = SSI_FRF_MOTO_MODE_2,
181  SPI_MODE_3 = SSI_FRF_MOTO_MODE_0,
182 } spi_mode_t;
184 #endif /* ndef DOXYGEN */
185 
186 #ifdef __cplusplus
187 }
188 #endif
189 
190 #endif /* PERIPH_CPU_H */
191 
SPI_CLK_400KHZ
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition: periph_cpu.h:653
SPI_MODE_3
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition: spi.h:161
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
spi_conf_t::ssi_base
unsigned long ssi_base
SSI base address.
Definition: periph_cpu.h:133
SPI_CLK_100KHZ
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition: periph_cpu.h:652
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
timer_conf_t::irqn
int irqn
Number of the higher timer IRQ channel.
Definition: periph_cpu.h:114
ADC_RES_6BIT
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition: adc.h:94
GPIO_IN_PD
@ GPIO_IN_PD
configure as input with pull-down resistor
Definition: gpio.h:120
gpio_dir_t
gpio_dir_t
Definition: periph_cpu.h:61
SPI_MODE_0
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition: spi.h:158
GPIO_OD
@ GPIO_OD
configure as output in open-drain mode without pull resistor
Definition: gpio.h:123
ADC_RES_14BIT
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition: adc.h:98
adc_res_t
adc_res_t
Possible ADC resolution settings.
Definition: adc.h:93
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
timer_conf_t::intbase
uint32_t intbase
Interrupt base of timer.
Definition: periph_cpu.h:116
GPIO_OUT
@ GPIO_OUT
configure as output in push-pull mode
Definition: gpio.h:122
spi_conf_t::clk
unsigned long clk
pin used for SCK
Definition: periph_cpu.h:137
ADC_RES_16BIT
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition: adc.h:99
spi_mode_t
spi_mode_t
Available SPI modes, defining the configuration of clock polarity and clock phase.
Definition: spi.h:157
ADC_RES_8BIT
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition: adc.h:95
GPIO_FALLING
@ GPIO_FALLING
emit interrupt on falling flank
Definition: periph_cpu.h:81
GPIO_IN_PU
@ GPIO_IN_PU
configure as input with pull-up resistor
Definition: gpio.h:121
GPIO_RISING
@ GPIO_RISING
emit interrupt on rising flank
Definition: periph_cpu.h:82
SPI_CLK_10MHZ
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition: periph_cpu.h:656
spi_clk_t
uint32_t spi_clk_t
SPI clock type.
Definition: periph_cpu.h:662
GPIO_IN
@ GPIO_IN
configure as input without pull resistor
Definition: gpio.h:119
spi_conf_t::gpio_sysctl
unsigned long gpio_sysctl
GPIO device in sysctl.
Definition: periph_cpu.h:134
timer_conf_t::sysctl
uint32_t sysctl
Address of timer system control.
Definition: periph_cpu.h:115
spi_conf_t::ssi_sysctl
unsigned long ssi_sysctl
SSI device in sysctl.
Definition: periph_cpu.h:132
PORT_F
@ PORT_F
port F
Definition: periph_cpu.h:41
SPI_CLK_5MHZ
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition: periph_cpu.h:655
gpio_flank_t
gpio_flank_t
Definition: periph_cpu.h:80
GPIO_OD_PU
@ GPIO_OD_PU
configure as output in open-drain mode with pull resistor enabled
Definition: gpio.h:125
spi_conf_t::gpio_port
unsigned long gpio_port
GPIO port.
Definition: periph_cpu.h:135
spi_conf_t::fss
unsigned long fss
pin used for FSS
Definition: periph_cpu.h:138
timer_conf_t::max
uint32_t max
Max tick value of timer.
Definition: periph_cpu.h:113
GPIO_BOTH
@ GPIO_BOTH
emit interrupt on both flanks
Definition: periph_cpu.h:83
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
GPIO_DIR_IN
@ GPIO_DIR_IN
configure pin as input
Definition: periph_cpu.h:62
spi_conf_t::rx
unsigned long rx
pin used for MISO
Definition: periph_cpu.h:139
spi_conf_t::tx
unsigned long tx
pin used for MOSI
Definition: periph_cpu.h:140
gpio_mode_t
gpio_mode_t
Available pin modes.
Definition: periph_cpu.h:70
ADC_RES_10BIT
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition: adc.h:96
ADC_RES_12BIT
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition: adc.h:97
gpio_t
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:91
SPI_CLK_1MHZ
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition: periph_cpu.h:654
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::mask
unsigned long mask
Pin mask.
Definition: periph_cpu.h:141
timer_conf_t::channels
int channels
Number of channels for the timer.
Definition: periph_cpu.h:117
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
SPI_MODE_1
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition: spi.h:159
GPIO_DIR_OUT
@ GPIO_DIR_OUT
configure pin as output
Definition: periph_cpu.h:63
SPI_MODE_2
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition: spi.h:160