periph_cpu_common.h

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/*
 * Copyright (C) 2015-2018 Freie Universität Berlin
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_COMMON_H
#define PERIPH_CPU_COMMON_H
 
#include "cpu.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define PROVIDES_PM_OFF
 
#define CPUID_ADDR          (&NRF_FICR->DEVICEID[0])
 
#define CPUID_LEN           (8U)
 
#ifdef CPU_MODEL_NRF52840XXAA
#define GPIO_PIN(x,y)       ((x << 5) | y)
#else
#define GPIO_PIN(x,y)       ((x & 0) | y)
#endif
 
/* The precise value matters where GPIO_UNDEF is set in registers like
 * PWM.PSEL.OUT where it is used in sign-extended form to get a UINT32_MAX */
#define GPIO_UNDEF          (UINT8_MAX)
 
#define GPIO_MODE(oe, ic, pr, dr)   (oe | (ic << 1) | (pr << 2) | (dr << 8))
 
#define SPI_HWCS(x)         (SPI_CS_UNDEF)
 
#define PERIPH_SPI_NEEDS_INIT_CS
#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
#define PERIPH_SPI_NEEDS_TRANSFER_REG
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
 
#ifndef DOXYGEN
 
#define HAVE_GPIO_T
typedef uint8_t gpio_t;
#define HAVE_GPIO_MODE_T
typedef enum {
    GPIO_IN       = GPIO_MODE(0, 0, 0, 0), 
    GPIO_IN_PD    = GPIO_MODE(0, 0, 1, 0), 
    GPIO_IN_PU    = GPIO_MODE(0, 0, 3, 0), 
    GPIO_IN_OD_PU = GPIO_MODE(0, 0, 3, 6), 
    GPIO_OUT      = GPIO_MODE(1, 1, 0, 0), 
    GPIO_OD       = (0xff),                
    GPIO_OD_PU    = (0xfe)                 
} gpio_mode_t;
#define HAVE_GPIO_FLANK_T
typedef enum {
    GPIO_FALLING = 2,       
    GPIO_RISING  = 1,       
    GPIO_BOTH    = 3        
} gpio_flank_t;
#endif /* ndef DOXYGEN */
 
typedef struct {
    NRF_TIMER_Type *dev;    
    uint8_t channels;       
    uint8_t bitmode;        
    uint8_t irqn;           
} timer_conf_t;
 
#ifndef DOXYGEN
 
#define HAVE_SPI_MODE_T
typedef enum {
    SPI_MODE_0 = 0,                                             
    SPI_MODE_1 = SPI_CONFIG_CPHA_Msk,                           
    SPI_MODE_2 = SPI_CONFIG_CPOL_Msk,                           
    SPI_MODE_3 = (SPI_CONFIG_CPOL_Msk | SPI_CONFIG_CPHA_Msk)    
} spi_mode_t;
#define HAVE_SPI_CLK_T
typedef enum {
    SPI_CLK_100KHZ = SPI_FREQUENCY_FREQUENCY_K125,  
    SPI_CLK_400KHZ = SPI_FREQUENCY_FREQUENCY_K500,  
    SPI_CLK_1MHZ   = SPI_FREQUENCY_FREQUENCY_M1,    
    SPI_CLK_5MHZ   = SPI_FREQUENCY_FREQUENCY_M4,    
    SPI_CLK_10MHZ  = SPI_FREQUENCY_FREQUENCY_M8     
} spi_clk_t;
#endif /* ndef DOXYGEN */
 
#define NWDT_TIME_LOWER_LIMIT          (1)
/* Set upper limit to the maximum possible value that could go in CRV register */
#define NWDT_TIME_UPPER_LIMIT          ((UINT32_MAX >> 15) * US_PER_MS + 1)
 
uint8_t gpio_int_get_exti(gpio_t pin);
 
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_COMMON_H */