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periph_conf.h
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/*
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* Copyright (C) 2014-2015,2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* targeted system core clock */
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#define CLOCK_CORECLOCK (84000000UL)
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/* external oscillator clock */
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#define CLOCK_EXT_OSC (12000000UL)
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/* define PLL configuration
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*
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* The values must fulfill this equation:
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* CORECLOCK = (EXT_OCS / PLL_DIV) * (PLL_MUL + 1)
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*/
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#define CLOCK_PLL_MUL (83)
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#define CLOCK_PLL_DIV (12)
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/* number of wait states before flash read and write operations */
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#define CLOCK_FWS (4)
/* 4 is save for 84MHz */
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#ifndef CLOCK_SCLK_XTAL
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#define CLOCK_SCLK_XTAL (0)
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#endif
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static
const
timer_conf_t
timer_config[] = {
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{ .
dev
= TC0, .id_ch0 = ID_TC0 },
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{ .dev = TC1, .id_ch0 = ID_TC3 }
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};
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#define TIMER_0_ISR isr_tc0
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#define TIMER_1_ISR isr_tc3
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#define RTT_FREQUENCY (1U)
/* 1Hz */
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static
const
uart_conf_t
uart_config[] = {
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{
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.
dev
= (Uart *)UART,
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.rx_pin =
GPIO_PIN
(
PA
, 8),
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.tx_pin =
GPIO_PIN
(
PA
, 9),
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.mux =
GPIO_MUX_A
,
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.pmc_id = ID_UART,
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.irqn = UART_IRQn
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},
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{
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.dev = (Uart *)USART0,
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.rx_pin =
GPIO_PIN
(
PA
, 10),
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.tx_pin =
GPIO_PIN
(
PA
, 11),
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.mux =
GPIO_MUX_A
,
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.pmc_id = ID_USART0,
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.irqn = USART0_IRQn
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},
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{
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.dev = (Uart *)USART1,
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.rx_pin =
GPIO_PIN
(
PA
, 12),
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.tx_pin =
GPIO_PIN
(
PA
, 13),
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.mux =
GPIO_MUX_A
,
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.pmc_id = ID_USART1,
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.irqn = USART1_IRQn
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},
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{
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.dev = (Uart *)USART3,
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.rx_pin =
GPIO_PIN
(
PD
, 5),
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.tx_pin =
GPIO_PIN
(
PD
, 4),
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.mux =
GPIO_MUX_B
,
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.pmc_id = ID_USART3,
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.irqn = USART3_IRQn
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}
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};
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/* define interrupt vectors */
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#define UART_0_ISR isr_uart
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#define UART_1_ISR isr_usart0
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#define UART_2_ISR isr_usart1
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#define UART_3_ISR isr_usart3
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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static
const
spi_conf_t
spi_config[] = {
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{
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.
dev
= SPI0,
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.id = ID_SPI0,
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.clk =
GPIO_PIN
(
PA
, 27),
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.mosi =
GPIO_PIN
(
PA
, 26),
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.miso =
GPIO_PIN
(
PA
, 25),
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.mux =
GPIO_MUX_A
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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static
const
pwm_chan_conf_t
pwm_chan[] = {
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{ .
pin
=
GPIO_PIN
(
PC
, 21), .hwchan = 4 },
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{ .pin =
GPIO_PIN
(
PC
, 22), .hwchan = 5 },
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{ .pin =
GPIO_PIN
(
PC
, 23), .hwchan = 6 },
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{ .pin =
GPIO_PIN
(
PC
, 24), .hwchan = 7 }
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};
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#define PWM_NUMOF (1U)
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#define PWM_CHAN_NUMOF ARRAY_SIZE(pwm_chan)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* PERIPH_CONF_H */
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PD
@ PD
port D
Definition:
periph_cpu_common.h:91
pwm_chan_conf_t
PWM channel configuration.
Definition:
periph_cpu.h:281
uart_conf_t
UART device configuration.
Definition:
periph_cpu.h:166
GPIO_MUX_A
@ GPIO_MUX_A
select peripheral function A
Definition:
periph_cpu_common.h:136
GPIO_MUX_B
@ GPIO_MUX_B
select peripheral function B
Definition:
periph_cpu_common.h:137
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition:
periph_cpu.h:167
timer_conf_t
Timer configuration.
Definition:
periph_cpu.h:288
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition:
periph_cpu.h:35
pwm_chan_conf_t::pin
gpio_t pin
pin used for pwm
Definition:
periph_cpu.h:283
PC
@ PC
port C
Definition:
periph_cpu_common.h:90
PA
@ PA
port A
Definition:
periph_cpu_common.h:88
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition:
periph_cpu.h:112
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition:
periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition:
periph_cpu.h:273
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