periph_conf.h
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1 /*
2  * Copyright (C) 2018 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C"
26 {
27 #endif
28 
33 static const clock_config_t clock_config = {
34  /*
35  * This configuration results in the system running with the internal clock
36  * with the following clock frequencies:
37  * Core: 8 MHz
38  * Bus: 8 MHz
39  * Flash: 8 MHz
40  */
41  .clkdiv1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV4(0),
42  /* unsure if this RTC load cap configuration is correct */
43  .rtc_clc = RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK,
44  /* Use the 32 kHz system oscillator output as ERCLK32K. */
45  .osc32ksel = SIM_SOPT1_OSC32KSEL(0),
46  .clock_flags =
47  KINETIS_CLOCK_RTCOSC_EN |
48  KINETIS_CLOCK_USE_FAST_IRC |
49  KINETIS_CLOCK_MCGIRCLK_EN | /* Used for LPUART clocking */
50  KINETIS_CLOCK_MCGIRCLK_STOP_EN |
51  0,
52  /* Using LIRC8M mode by default */
53  .default_mode = KINETIS_MCG_MODE_LIRC8M,
54  /* The crystal connected to EXTAL0 is 32.768 kHz */
55  .erc_range = KINETIS_MCG_ERC_RANGE_LOW,
56  .osc_clc = 0, /* no load cap configuration, rtc_clc overrides this value on KL43Z */
57  .fcrdiv = MCG_SC_FCRDIV(0), /* LIRC_DIV1 divide by 1 => 8 MHz */
58  .lirc_div2 = MCG_MC_LIRC_DIV2(0), /* LIRC_DIV2 divide by 1 => 8 MHz */
59 };
60 #define CLOCK_CORECLOCK ( 8000000ul)
61 #define CLOCK_MCGIRCLK ( 8000000ul)
62 #define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 1)
63 
69 #define PIT_NUMOF (1U)
70 #define PIT_CONFIG { \
71  { \
72  .prescaler_ch = 0, \
73  .count_ch = 1, \
74  }, \
75 }
76 #define LPTMR_NUMOF (1U)
77 #define LPTMR_CONFIG { \
78  { \
79  .dev = LPTMR0, \
80  .irqn = LPTMR0_IRQn, \
81  .src = 2, \
82  .base_freq = 32768u, \
83  }, \
84  }
85 #define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
86 
87 #define PIT_BASECLOCK (CLOCK_BUSCLOCK)
88 #define PIT_ISR_0 isr_pit1
89 #define LPTMR_ISR_0 isr_lptmr0
90 
96 static const uart_conf_t uart_config[] = {
97  {
98  .dev = LPUART0,
99  .freq = CLOCK_MCGIRCLK,
100  .pin_rx = GPIO_PIN(PORT_A, 1),
101  .pin_tx = GPIO_PIN(PORT_A, 2),
102  .pcr_rx = PORT_PCR_MUX(2),
103  .pcr_tx = PORT_PCR_MUX(2),
104  .irqn = LPUART0_IRQn,
105  .scgc_addr = &SIM->SCGC5,
106  .scgc_bit = SIM_SCGC5_LPUART0_SHIFT,
107  .mode = UART_MODE_8N1,
108  .type = KINETIS_LPUART,
109  },
110 };
111 #define UART_NUMOF ARRAY_SIZE(uart_config)
112 #define LPUART_0_ISR isr_lpuart0
113 /* Use MCGIRCLK (internal reference 4 MHz clock) */
114 #define LPUART_0_SRC 3
115 
121 static const adc_conf_t adc_config[] = {
122  /* dev, pin, channel */
123  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8, .avg = ADC_AVG_MAX }, /* Arduino A0 */
124  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9, .avg = ADC_AVG_MAX }, /* Arduino A1 */
125  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 2), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A2 */
126  { .dev = ADC0, .pin = GPIO_PIN(PORT_B, 3), .chan = 4, .avg = ADC_AVG_MAX }, /* Arduino A3 */
127  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 2), .chan = 11, .avg = ADC_AVG_MAX }, /* Arduino A4 */
128  { .dev = ADC0, .pin = GPIO_PIN(PORT_C, 1), .chan = 15, .avg = ADC_AVG_MAX }, /* Arduino A5 */
129 };
130 
131 #define ADC_NUMOF ARRAY_SIZE(adc_config)
132 /*
133  * KL43Z ADC reference settings:
134  * 0: VREFH/VREFL external pin pair
135  * 1: VDDA/VSSA supply pins
136  * 2-3: reserved
137  */
138 #define ADC_REF_SETTING 0
139 
145 static const i2c_conf_t i2c_config[] = {
146  {
147  .i2c = I2C0,
148  .scl_pin = GPIO_PIN(PORT_E, 24),
149  .sda_pin = GPIO_PIN(PORT_E, 25),
150  .freq = CLOCK_CORECLOCK,
151  .speed = I2C_SPEED_FAST,
152  .irqn = I2C0_IRQn,
153  .scl_pcr = (PORT_PCR_MUX(5)),
154  .sda_pcr = (PORT_PCR_MUX(5)),
155  },
156  {
157  .i2c = I2C1,
158  .scl_pin = GPIO_PIN(PORT_E, 1),
159  .sda_pin = GPIO_PIN(PORT_E, 0),
160  .freq = CLOCK_CORECLOCK,
161  .speed = I2C_SPEED_FAST,
162  .irqn = I2C1_IRQn,
163  .scl_pcr = (PORT_PCR_MUX(6)),
164  .sda_pcr = (PORT_PCR_MUX(6)),
165  },
166 };
167 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
168 #define I2C_0_ISR isr_i2c0
169 #define I2C_1_ISR isr_i2c1
170 
172 #ifdef __cplusplus
173 }
174 #endif
175 
176 #endif /* PERIPH_CONF_H */
177 
PORT_E
@ PORT_E
port E
Definition: periph_cpu.h:40
PORT_C
@ PORT_C
port C
Definition: periph_cpu.h:38
CLOCK_CORECLOCK
#define CLOCK_CORECLOCK
GCLK reference speed.
Definition: periph_conf.h:32
adc_conf_t::dev
ADC_TypeDef * dev
ADC device used.
Definition: periph_cpu.h:75
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
UART_MODE_8N1
@ UART_MODE_8N1
8 data bits, no parity, 1 stop bit
Definition: periph_cpu.h:286
i2c_conf_t::i2c
I2C_Type * i2c
Pointer to hardware module registers.
Definition: periph_cpu.h:451
KINETIS_LPUART
@ KINETIS_LPUART
Kinetis Low-power UART (LPUART) module type.
Definition: periph_cpu.h:508
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
I2C_SPEED_FAST
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition: i2c.h:178
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
ADC_AVG_MAX
#define ADC_AVG_MAX
Maximum hardware averaging (32 samples)
Definition: periph_cpu.h:366