Configuration of CPU peripherals for the Atmel SAM D21 Xplained Pro board.
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Configuration of CPU peripherals for the Atmel SAM D21 Xplained Pro board.
- Author
- Travis Griggs travi.nosp@m.sgri.nosp@m.ggs@g.nosp@m.mail.nosp@m..com
-
Dan Evans photo.nosp@m.nthu.nosp@m.nder@.nosp@m.gmai.nosp@m.l.com
Definition in file periph_conf.h.
#include <stdint.h>
#include "cpu.h"
#include "periph_cpu.h"
Go to the source code of this file.
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There are three choices for selection of CORECLOCK:
- usage of the 48 MHz DFLL fed by external oscillator running at 32 kHz
- usage of the PLL fed by the internal 8MHz oscillator divided by 8
- usage of the internal 8MHz oscillator directly, divided by N if needed
The PLL option allows for the usage of a wider frequency range and a more stable clock with less jitter. This is why this option is default.
The target frequency is computed from the PLL multiplier and the PLL divisor. Use the following formula to compute your values:
CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL frequency is 96MHz. So PLL_MULL must be between 31 and 95!
The internal Oscillator used directly can lead to a slightly better power efficiency to the cost of a less stable clock. Use this option when you know what you are doing! The actual core frequency is adjusted as follows:
CORECLOCK = 8MHz / DIV
NOTE: A core clock frequency below 1MHz is not recommended
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#define | CLOCK_USE_PLL (1) |
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#define | CLOCK_USE_XOSC32_DFLL (0) |
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#define | GEN2_ULP32K (0) |
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#define | CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */ |
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#define | CLOCK_PLL_DIV (1U) /* adjust to your needs */ |
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#define | CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV) |
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#define | TIMER_0_MAX_VALUE 0xffff |
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#define | TIMER_0_ISR isr_tc3 |
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#define | TIMER_1_ISR isr_tc4 |
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#define | TIMER_NUMOF ARRAY_SIZE(timer_config) |
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static const tc32_conf_t | timer_config [] |
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#define | UART_0_ISR isr_sercom3 |
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#define | UART_1_ISR isr_sercom4 |
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#define | UART_2_ISR isr_sercom5 |
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#define | UART_NUMOF ARRAY_SIZE(uart_config) |
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static const uart_conf_t | uart_config [] |
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#define | PWM_0_EN 1 |
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#define | PWM_1_EN 0 |
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#define | PWM_2_EN 0 |
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#define | PWM_NUMOF ARRAY_SIZE(pwm_config) |
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static const pwm_conf_chan_t | pwm_chan0_config [] |
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static const pwm_conf_t | pwm_config [] |
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#define | RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */ |
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#define | ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512 |
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#define | ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND |
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#define | ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X |
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#define | ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V |
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#define | ADC_NUMOF ARRAY_SIZE(adc_channels) |
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static const adc_conf_chan_t | adc_channels [] |
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#define | DAC_CLOCK SAM0_GCLK_1MHZ |
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#define | DAC_VREF DAC_CTRLB_REFSEL_AVCC |
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◆ adc_channels
◆ i2c_config
Initial value:= {
{
.dev = &(SERCOM2->I2CM),
}
}
Definition at line 305 of file periph_conf.h.
◆ pwm_chan0_config
◆ pwm_config
◆ timer_config
Initial value:= {
{
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
.flags = TC_CTRLA_MODE_COUNT16,
},
{
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
.flags = TC_CTRLA_MODE_COUNT32,
}
}
Definition at line 100 of file periph_conf.h.