cfg_timer_tim5.h
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1 /*
2  * Copyright (C) 2019 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CFG_TIMER_TIM5_H
20 #define CFG_TIMER_TIM5_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 static const timer_conf_t timer_config[] = {
33  {
34  .dev = TIM5,
35  .max = 0xffffffff,
36 #if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
37  .rcc_mask = RCC_APB1ENR1_TIM5EN,
38 #else
39  .rcc_mask = RCC_APB1ENR_TIM5EN,
40 #endif
41  .bus = APB1,
42  .irqn = TIM5_IRQn
43  }
44 };
45 
46 #define TIMER_0_ISR isr_tim5
47 
48 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
49 
51 #ifdef __cplusplus
52 }
53 #endif
54 
55 #endif /* CFG_TIMER_TIM5_H */
56 
timer_conf_t
Timer configuration.
Definition: periph_cpu.h:288
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition: periph_cpu.h:112
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176