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cfg_timer_tim5.h
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/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CFG_TIMER_TIM5_H
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#define CFG_TIMER_TIM5_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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static
const
timer_conf_t
timer_config[] = {
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{
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.
dev
= TIM5,
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.max = 0xffffffff,
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#if defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5)
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.rcc_mask = RCC_APB1ENR1_TIM5EN,
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#else
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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#endif
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.bus =
APB1
,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* CFG_TIMER_TIM5_H */
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timer_conf_t
Timer configuration.
Definition:
periph_cpu.h:288
timer_conf_t::dev
uint32_t dev
Address of timer base.
Definition:
periph_cpu.h:112
APB1
@ APB1
APB1 bus.
Definition:
periph_cpu.h:176
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