periph_cpu.h

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/*
 * Copyright (C) 2019 ML!PA Consulting GmbH
 *
 * This file is subject to the terms and conditions of the GNU Lesser
 * General Public License v2.1. See the file LICENSE in the top level
 * directory for more details.
 */
 
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
 
#include <limits.h>
 
#include "macros/units.h"
#include "periph_cpu_common.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define SAM0_DFLL_FREQ_HZ       MHZ(48)
 
#define SAM0_XOSC_FREQ_HZ       (XOSC0_FREQUENCY ? XOSC0_FREQUENCY : XOSC1_FREQUENCY)
 
#define SAM0_DPLL_FREQ_MIN_HZ   MHZ(96)
 
#define SAM0_DPLL_FREQ_MAX_HZ   MHZ(20)
 
#define PM_NUM_MODES        (3)
 
enum {
    SAM0_GCLK_MAIN = 0,                 
    SAM0_GCLK_32KHZ,                    
    SAM0_GCLK_TIMER,                    
    SAM0_GCLK_PERIPH,                   
};
#define SAM0_GCLK_8MHZ      SAM0_GCLK_TIMER
#define SAM0_GCLK_48MHZ     SAM0_GCLK_PERIPH
 
#define SPI_HWCS(x)     (UINT_MAX - 1)
 
#ifndef DOXYGEN
#define HAVE_ADC_RES_T
typedef enum {
    ADC_RES_6BIT  = 0xff,                       
    ADC_RES_8BIT  = ADC_CTRLB_RESSEL_8BIT,      
    ADC_RES_10BIT = ADC_CTRLB_RESSEL_10BIT,     
    ADC_RES_12BIT = ADC_CTRLB_RESSEL_12BIT,     
    ADC_RES_14BIT = 0xfe,                       
    ADC_RES_16BIT = 0xfd                        
} adc_res_t;
#endif /* DOXYGEN */
 
#define DAC_RES_BITS        (12)
 
#define DAC_NUMOF           (2)
 
#define RTT_MAX_VALUE       (0xffffffff)
#define RTT_CLOCK_FREQUENCY (32768U)                      /* in Hz */
#define RTT_MIN_FREQUENCY   (RTT_CLOCK_FREQUENCY / 1024U) /* in Hz */
#define RTT_MAX_FREQUENCY   (RTT_CLOCK_FREQUENCY)         /* in Hz */
 
static const gpio_t rtc_tamper_pins[RTC_NUM_OF_TAMPERS] = {
    GPIO_PIN(PB, 0), GPIO_PIN(PB, 2), GPIO_PIN(PA, 2),
    GPIO_PIN(PC, 0), GPIO_PIN(PC, 1)
};
 
struct sam0_aux_cfg_mapping {
    /* config word 0 */
    uint32_t bod33_disable              :  1; 
    uint32_t bod33_level                :  8; 
    uint32_t bod33_action               :  2; 
    uint32_t bod33_hysteresis           :  4; 
    const uint32_t bod12_calibration    : 11; 
    uint32_t nvm_boot_size              :  4; 
    uint32_t reserved_0                 :  2; 
    /* config word 1 */
    uint32_t smart_eeprom_blocks        :  4; 
    uint32_t smart_eeprom_page_size     :  3; 
    uint32_t ram_eccdis                 :  1; 
    uint32_t reserved_1                 :  8; 
    uint32_t wdt_enable                 :  1; 
    uint32_t wdt_always_on              :  1; 
    uint32_t wdt_period                 :  4; 
    uint32_t wdt_window                 :  4; 
    uint32_t wdt_ewoffset               :  4; 
    uint32_t wdt_window_enable          :  1; 
    uint32_t reserved_2                 :  1; 
    /* config word 2 */
    uint32_t nvm_locks;                       
    /* config word 3 */
    uint32_t user_page;                       
    /* config word 4 */
    uint32_t reserved_3;                      
    /* config words 5,6,7 */
    uint32_t user_pages[3];                   
};
#ifdef __cplusplus
}
#endif
 
#endif /* PERIPH_CPU_H */