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periph_conf.h
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1 /*
2  * Copyright (C) 2016 Freie Universität Berlin
3  * 2016-2018 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
24 #ifndef PERIPH_CONF_H
25 #define PERIPH_CONF_H
26 
27 #include "periph_cpu.h"
28 #include "periph_conf_common.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 static const uart_conf_t uart_config[] = {
39  {
40  .dev = &SERCOM5->USART,
41  .rx_pin = GPIO_PIN(PB,23), /* ARDUINO_PIN_13, RX Pin */
42  .tx_pin = GPIO_PIN(PB,22), /* ARDUINO_PIN_14, TX Pin */
43 #ifdef MODULE_PERIPH_UART_HW_FC
44  .rts_pin = GPIO_UNDEF,
45  .cts_pin = GPIO_UNDEF,
46 #endif
47  .mux = GPIO_MUX_D,
48  .rx_pad = UART_PAD_RX_3,
49  .tx_pad = UART_PAD_TX_2,
50  .flags = UART_FLAG_NONE,
51  .gclk_src = SAM0_GCLK_MAIN,
52  },
53  { /* LoRa module */
54  .dev = &SERCOM4->USART,
55  .rx_pin = GPIO_PIN(PA,15),
56  .tx_pin = GPIO_PIN(PA,12),
57 #ifdef MODULE_PERIPH_UART_HW_FC
58  .rts_pin = GPIO_UNDEF,
59  .cts_pin = GPIO_UNDEF,
60 #endif
61  .mux = GPIO_MUX_D,
62  .rx_pad = UART_PAD_RX_3,
63  .tx_pad = UART_PAD_TX_0,
64  .flags = UART_FLAG_NONE,
65  .gclk_src = SAM0_GCLK_MAIN,
66  },
67 };
68 
69 /* interrupt function name mapping */
70 #define UART_0_ISR isr_sercom5
71 #define UART_1_ISR isr_sercom4
72 
73 #define UART_NUMOF ARRAY_SIZE(uart_config)
74 
80 static const spi_conf_t spi_config[] = {
81  {
82  .dev = &SERCOM1->SPI,
83  .miso_pin = GPIO_PIN(PA, 19), /* ARDUINO_PIN_8, SERCOM1-MISO */
84  .mosi_pin = GPIO_PIN(PA, 16), /* ARDUINO_PIN_10, SERCOM1-MOSI */
85  .clk_pin = GPIO_PIN(PA, 17), /* ARDUINO_PIN_9, SERCOM1-SCK */
86  .miso_mux = GPIO_MUX_C,
87  .mosi_mux = GPIO_MUX_C,
88  .clk_mux = GPIO_MUX_C,
89  .miso_pad = SPI_PAD_MISO_3,
90  .mosi_pad = SPI_PAD_MOSI_0_SCK_1,
91  .gclk_src = SAM0_GCLK_MAIN,
92  }
93 };
94 
95 #define SPI_NUMOF ARRAY_SIZE(spi_config)
96 
98 #ifdef __cplusplus
99 }
100 #endif
101 
102 #endif /* PERIPH_CONF_H */
103 
UART_PAD_RX_3
@ UART_PAD_RX_3
select pad 3
Definition: periph_cpu_common.h:154
SAM0_GCLK_MAIN
@ SAM0_GCLK_MAIN
48 MHz main clock
Definition: periph_cpu.h:59
UART_PAD_TX_0
@ UART_PAD_TX_0
select pad 0
Definition: periph_cpu_common.h:161
UART_FLAG_NONE
@ UART_FLAG_NONE
No flags set.
Definition: periph_cpu_common.h:171
PB
@ PB
port B
Definition: periph_cpu_common.h:89
UART_PAD_TX_2
@ UART_PAD_TX_2
select pad 2
Definition: periph_cpu_common.h:162
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
GPIO_MUX_C
@ GPIO_MUX_C
select peripheral function C
Definition: periph_cpu_common.h:138
SPI_PAD_MOSI_0_SCK_1
@ SPI_PAD_MOSI_0_SCK_1
use pad 0 for MOSI, pad 1 for SCK
Definition: periph_cpu_common.h:337
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
SPI_PAD_MISO_3
@ SPI_PAD_MISO_3
use pad 0 for MISO line
Definition: periph_cpu_common.h:330
GPIO_MUX_D
@ GPIO_MUX_D
select peripheral function D
Definition: periph_cpu_common.h:139
PA
@ PA
port A
Definition: periph_cpu_common.h:88
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273