periph_conf.h
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1 /*
2  * Copyright (C) 2020 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* Add specific clock configuration (HSE, LSE) for this board here */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 #include "cfg_i2c1_pb6_pb7.h"
30 #include "cfg_rtt_default.h"
31 #include "cfg_timer_tim2.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
41 static const uart_conf_t uart_config[] = {
42  {
43  .dev = USART2,
44  .rcc_mask = RCC_APB1ENR_USART2EN,
45  .rx_pin = GPIO_PIN(PORT_A, 15),
46  .tx_pin = GPIO_PIN(PORT_A, 2),
47  .rx_af = GPIO_AF4,
48  .tx_af = GPIO_AF4,
49  .bus = APB1,
50  .irqn = USART2_IRQn,
51  .type = STM32_USART,
52  .clk_src = 0, /* Use APB clock */
53  }
54 };
55 
56 #define UART_0_ISR (isr_usart2)
57 
58 #define UART_NUMOF ARRAY_SIZE(uart_config)
59 
65 static const spi_conf_t spi_config[] = {
66  {
67  .dev = SPI1,
68  .mosi_pin = GPIO_PIN(PORT_B, 5),
69  .miso_pin = GPIO_PIN(PORT_B, 4),
70  .sclk_pin = GPIO_PIN(PORT_B, 3),
71  .cs_pin = GPIO_UNDEF,
72  .mosi_af = GPIO_AF0,
73  .miso_af = GPIO_AF0,
74  .sclk_af = GPIO_AF0,
75  .cs_af = GPIO_AF0,
76  .rccmask = RCC_APB2ENR_SPI1EN,
77  .apbbus = APB2
78  }
79 };
80 
81 #define SPI_NUMOF ARRAY_SIZE(spi_config)
82 
88 static const adc_conf_t adc_config[] = {
89  { GPIO_PIN(PORT_A, 0), 0 }, /* Pin A0 */
90  { GPIO_PIN(PORT_A, 1), 1 }, /* Pin A1 */
91  { GPIO_PIN(PORT_A, 3), 3 }, /* Pin A2 */
92  { GPIO_PIN(PORT_A, 4), 4 }, /* Pin A3 */
93  { GPIO_PIN(PORT_A, 5), 5 }, /* Pin A4 */
94  { GPIO_PIN(PORT_A, 6), 6 }, /* Pin A5 */
95  { GPIO_PIN(PORT_A, 7), 7 }, /* Pin A6 */
96 };
97 
98 #define ADC_NUMOF ARRAY_SIZE(adc_config)
99 
101 #ifdef __cplusplus
102 }
103 #endif
104 
105 #endif /* PERIPH_CONF_H */
106 
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: periph_cpu_common.h:90
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition: periph_cpu.h:583
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
adc_conf_t
ADC device configuration.
Definition: periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
GPIO_AF0
@ GPIO_AF0
use alternate function 0
Definition: periph_cpu_common.h:86
cfg_timer_tim2.h
Common configuration for STM32 Timer peripheral based on TIM2.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
cfg_i2c1_pb6_pb7.h
Common configuration for STM32 I2C.
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176