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periph_conf.h
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/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* Add specific clock configuration (HSE, LSE) for this board here */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "
cfg_i2c1_pb6_pb7.h
"
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#include "cfg_rtt_default.h"
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#include "
cfg_timer_tim2.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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static
const
uart_conf_t
uart_config[] = {
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{
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.
dev
= USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin =
GPIO_PIN
(
PORT_A
, 15),
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.tx_pin =
GPIO_PIN
(
PORT_A
, 2),
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.rx_af =
GPIO_AF4
,
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.tx_af =
GPIO_AF4
,
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.bus =
APB1
,
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.irqn = USART2_IRQn,
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.type =
STM32_USART
,
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.clk_src = 0,
/* Use APB clock */
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}
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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static
const
spi_conf_t
spi_config[] = {
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{
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.
dev
= SPI1,
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.mosi_pin =
GPIO_PIN
(
PORT_B
, 5),
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.miso_pin =
GPIO_PIN
(
PORT_B
, 4),
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.sclk_pin =
GPIO_PIN
(
PORT_B
, 3),
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.cs_pin =
GPIO_UNDEF
,
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.mosi_af =
GPIO_AF0
,
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.miso_af =
GPIO_AF0
,
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.sclk_af =
GPIO_AF0
,
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.cs_af =
GPIO_AF0
,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus =
APB2
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}
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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static
const
adc_conf_t
adc_config[] = {
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{
GPIO_PIN
(
PORT_A
, 0), 0 },
/* Pin A0 */
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{
GPIO_PIN
(
PORT_A
, 1), 1 },
/* Pin A1 */
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{
GPIO_PIN
(
PORT_A
, 3), 3 },
/* Pin A2 */
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{
GPIO_PIN
(
PORT_A
, 4), 4 },
/* Pin A3 */
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{
GPIO_PIN
(
PORT_A
, 5), 5 },
/* Pin A4 */
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{
GPIO_PIN
(
PORT_A
, 6), 6 },
/* Pin A5 */
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{
GPIO_PIN
(
PORT_A
, 7), 7 },
/* Pin A6 */
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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#ifdef __cplusplus
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}
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#endif
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#endif
/* PERIPH_CONF_H */
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GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition:
periph_cpu_common.h:90
PORT_A
@ PORT_A
port A
Definition:
periph_cpu.h:36
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition:
periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition:
periph_cpu.h:166
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition:
periph_cpu.h:583
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition:
periph_cpu.h:167
adc_conf_t
ADC device configuration.
Definition:
periph_cpu.h:74
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition:
periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition:
periph_cpu.h:177
GPIO_AF0
@ GPIO_AF0
use alternate function 0
Definition:
periph_cpu_common.h:86
cfg_timer_tim2.h
Common configuration for STM32 Timer peripheral based on TIM2.
PORT_B
@ PORT_B
port B
Definition:
periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition:
periph_cpu.h:465
spi_conf_t
SPI configuration structure type.
Definition:
periph_cpu.h:273
cfg_i2c1_pb6_pb7.h
Common configuration for STM32 I2C.
APB1
@ APB1
APB1 bus.
Definition:
periph_cpu.h:176
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