periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 /* Add specific clock configuration (HSE, LSE) for this board here */
23 #ifndef CONFIG_BOARD_HAS_LSE
24 #define CONFIG_BOARD_HAS_LSE 1
25 #endif
26 
27 #include "periph_cpu.h"
28 #include "clk_conf.h"
29 #include "cfg_rtt_default.h"
30 #include "cfg_timer_tim2.h"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
40 static const uart_conf_t uart_config[] = {
41  {
42  .dev = USART2,
43  .rcc_mask = RCC_APB1ENR1_USART2EN,
44  .rx_pin = GPIO_PIN(PORT_D, 6),
45  .tx_pin = GPIO_PIN(PORT_A, 2),
46  .rx_af = GPIO_AF7,
47  .tx_af = GPIO_AF7,
48  .bus = APB1,
49  .irqn = USART2_IRQn,
50 #ifdef MODULE_PERIPH_UART_HW_FC
51  .cts_pin = GPIO_UNDEF,
52  .rts_pin = GPIO_UNDEF,
53  .cts_af = GPIO_AF7,
54  .rts_af = GPIO_AF7,
55 #endif
56  .type = STM32_USART,
57  .clk_src = 0, /* Use APB clock */
58  },
59  { /* Arduino pinout RX/TX pins on D0/D1 */
60  .dev = LPUART1,
61  .rcc_mask = RCC_APB1ENR2_LPUART1EN,
62  .rx_pin = GPIO_PIN(PORT_G, 8),
63  .tx_pin = GPIO_PIN(PORT_G, 7),
64  .rx_af = GPIO_AF8,
65  .tx_af = GPIO_AF8,
66  .bus = APB12,
67  .irqn = LPUART1_IRQn,
68 #ifdef MODULE_PERIPH_UART_HW_FC
69  .cts_pin = GPIO_UNDEF,
70  .rts_pin = GPIO_UNDEF,
71  .cts_af = GPIO_AF7,
72  .rts_af = GPIO_AF7,
73 #endif
74  .type = STM32_LPUART,
75  .clk_src = 0,
76  },
77  { /* STMod+/PMOD connectors */
78  .dev = USART1,
79  .rcc_mask = RCC_APB2ENR_USART1EN,
80  .rx_pin = GPIO_PIN(PORT_B, 6),
81  .tx_pin = GPIO_PIN(PORT_G, 10),
82  .rx_af = GPIO_AF7,
83  .tx_af = GPIO_AF7,
84  .bus = APB2,
85  .irqn = USART1_IRQn,
86 #ifdef MODULE_PERIPH_UART_HW_FC
87  .cts_pin = GPIO_PIN(PORT_G, 11),
88  .rts_pin = GPIO_PIN(PORT_G, 12),
89  .cts_af = GPIO_AF7,
90  .rts_af = GPIO_AF7,
91 #endif
92  .type = STM32_USART,
93  .clk_src = 0, /* Use APB clock */
94  }
95 };
96 
97 #define UART_0_ISR (isr_usart2)
98 #define UART_1_ISR (isr_lpuart1)
99 #define UART_2_ISR (isr_usart1)
100 
101 #define UART_NUMOF ARRAY_SIZE(uart_config)
102 
108 static const i2c_conf_t i2c_config[] = {
109  {
110  .dev = I2C1,
111  .speed = I2C_SPEED_NORMAL,
112  .scl_pin = GPIO_PIN(PORT_B, 8),
113  .sda_pin = GPIO_PIN(PORT_B, 7),
114  .scl_af = GPIO_AF4,
115  .sda_af = GPIO_AF4,
116  .bus = APB1,
117  .rcc_mask = RCC_APB1ENR1_I2C1EN,
118  .irqn = I2C1_ER_IRQn
119  },
120 };
121 
122 #define I2C_0_ISR isr_i2c1_er
123 
124 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
125 
131 static const spi_conf_t spi_config[] = {
132  {
133  .dev = SPI1,
134  .mosi_pin = GPIO_PIN(PORT_B, 5),
135  .miso_pin = GPIO_PIN(PORT_B, 4),
136  .sclk_pin = GPIO_PIN(PORT_A, 5),
137  .cs_pin = GPIO_UNDEF,
138  .mosi_af = GPIO_AF5,
139  .miso_af = GPIO_AF5,
140  .sclk_af = GPIO_AF5,
141  .cs_af = GPIO_AF5,
142  .rccmask = RCC_APB2ENR_SPI1EN,
143  .apbbus = APB2
144  }
145 };
146 
147 #define SPI_NUMOF ARRAY_SIZE(spi_config)
148 
150 #ifdef __cplusplus
151 }
152 #endif
153 
154 #endif /* PERIPH_CONF_H */
155 
GPIO_AF8
@ GPIO_AF8
use alternate function 8
Definition: periph_cpu_common.h:94
GPIO_AF4
@ GPIO_AF4
use alternate function 4
Definition: periph_cpu_common.h:90
I2C_SPEED_NORMAL
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition: i2c.h:177
GPIO_AF5
@ GPIO_AF5
use alternate function 5
Definition: periph_cpu_common.h:91
PORT_A
@ PORT_A
port A
Definition: periph_cpu.h:36
PORT_D
@ PORT_D
port D
Definition: periph_cpu.h:39
GPIO_UNDEF
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Definition: periph_cpu_common.h:52
uart_conf_t
UART device configuration.
Definition: periph_cpu.h:166
STM32_USART
@ STM32_USART
STM32 USART module type.
Definition: periph_cpu.h:583
uart_conf_t::dev
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
GPIO_AF7
@ GPIO_AF7
use alternate function 7
Definition: periph_cpu_common.h:93
GPIO_PIN
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
APB2
@ APB2
APB2 bus.
Definition: periph_cpu.h:177
STM32_LPUART
@ STM32_LPUART
STM32 Low-power UART (LPUART) module type.
Definition: periph_cpu.h:584
i2c_conf_t
I2C configuration options.
Definition: periph_cpu.h:128
cfg_timer_tim2.h
Common configuration for STM32 Timer peripheral based on TIM2.
PORT_B
@ PORT_B
port B
Definition: periph_cpu.h:37
spi_conf_t::dev
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:465
PORT_G
@ PORT_G
port G
Definition: periph_cpu.h:42
spi_conf_t
SPI configuration structure type.
Definition: periph_cpu.h:273
i2c_conf_t::dev
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:247
APB1
@ APB1
APB1 bus.
Definition: periph_cpu.h:176